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Caleb Begly
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Add autoinst_multidim_rename test and fix for issue veripool#1848 
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Diff for: ‎tests/autoinst_multidim_rename.sv

+44
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,44 @@
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module parent(/*AUTOARG*/);
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input [31:0][7:0] data_in;
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output [4:0] meta_out;
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output [4:0] meta_out_no_rename;
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output [31:0][7:0] data_out;
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/*AUTOWIRE*/
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/* child1 AUTO_TEMPLATE (
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.data_out (child1_out[][]),
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.meta_out (child1_meta_out[]),
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); */
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child1 U1 (
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/*AUTOINST*/
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)
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/* child2 AUTO_TEMPLATE (
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.data_in (child1_out[][]),
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.meta_in (child1_meta_out[]),
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); */
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child2 U2 (
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/*AUTOINST*/
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)
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endmodule
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module child1(/*AUTOARG*/);
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input [31:0][7:0] data_in;
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output [31:0][7:0] data_out;
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output [4:0] meta_out;
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endmodule
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module child2(/*AUTOARG*/);
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input [31:0][7:0] data_in;
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input [4:0] meta_in;
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output [31:0][7:0] data_out;
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output [4:0] meta_out_no_rename;
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endmodule
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// Local Variables:
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// verilog-auto-inst-vector:nil
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// End:

Diff for: ‎tests_ok/autoinst_multidim_rename.sv

+72
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,72 @@
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module parent(/*AUTOARG*/
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// Outputs
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meta_out, meta_out_no_rename, data_out,
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// Inputs
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data_in
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);
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input [31:0][7:0] data_in;
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output [4:0] meta_out;
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output [4:0] meta_out_no_rename;
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output [31:0][7:0] data_out;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [4:0] child1_meta_out; // From U1 of child1.v
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wire [31:0] [7:0] child1_out; // From U1 of child1.v
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// End of automatics
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/* child1 AUTO_TEMPLATE (
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.data_out (child1_out[][]),
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.meta_out (child1_meta_out[]),
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); */
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child1 U1 (
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/*AUTOINST*/
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// Outputs
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.data_out (child1_out/*[31:0][7:0]*/), // Templated
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.meta_out (child1_meta_out[4:0]), // Templated
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// Inputs
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.data_in (data_in/*[31:0][7:0]*/));
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/* child2 AUTO_TEMPLATE (
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.data_in (child1_out[][]),
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.meta_in (child1_meta_out[]),
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) */
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child2 U2 (
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/*AUTOINST*/
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// Outputs
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.data_out (data_out/*[31:0][7:0]*/),
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.meta_out_no_rename (meta_out_no_rename),
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// Inputs
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.data_in (child1_out/*[31:0][7:0]*/), // Templated
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.meta_in (child1_meta_out[4:0])); // Templated
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endmodule
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module child1(/*AUTOARG*/
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// Outputs
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data_out, meta_out,
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// Inputs
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data_in
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)
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input [31:0][7:0] data_in;
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output [31:0][7:0] data_out;
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output [4:0] meta_out;
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endmodule
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module child2(/*AUTOARG*/
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// Outputs
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data_out, meta_out_no_rename,
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// Inputs
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data_in, meta_in
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);
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input [31:0][7:0] data_in;
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input [4:0] meta_in;
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output [31:0][7:0] data_out;
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output [4:0] meta_out_no_rename;
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endmodule
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// Local Variables:
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// verilog-auto-inst-vector:nil
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// End:

Diff for: ‎verilog-mode.el

+24-12
Original file line numberDiff line numberDiff line change
@@ -12256,15 +12256,7 @@ If PAR-VALUES replace final strings with these parameter values."
1225612256
(vl-memory (verilog-sig-memory port-st))
1225712257
(vl-mbits (if (verilog-sig-multidim port-st)
1225812258
(verilog-sig-multidim-string port-st) ""))
12259-
(vl-bits (if (or (eq verilog-auto-inst-vector t)
12260-
(and (eq verilog-auto-inst-vector `unsigned)
12261-
(not (verilog-sig-signed port-st)))
12262-
(not (assoc port (verilog-decls-get-signals moddecls)))
12263-
(not (equal (verilog-sig-bits port-st)
12264-
(verilog-sig-bits
12265-
(assoc port (verilog-decls-get-signals moddecls))))))
12266-
(or (verilog-sig-bits port-st) "")
12267-
""))
12259+
(vl-bits (or (verilog-sig-bits port-st) ""))
1226812260
(case-fold-search nil)
1226912261
(check-values par-values)
1227012262
tpl-net dflt-bits)
@@ -12290,16 +12282,26 @@ If PAR-VALUES replace final strings with these parameter values."
1229012282
vl-mbits (verilog-simplify-range-expression vl-mbits)
1229112283
vl-memory (when vl-memory (verilog-simplify-range-expression vl-memory))
1229212284
vl-width (verilog-make-width-expression vl-bits))) ; Not in the loop for speed
12285+
(setq auto-inst-vector
12286+
(if (or (eq verilog-auto-inst-vector t)
12287+
(and (eq verilog-auto-inst-vector `unsigned)
12288+
(not (verilog-sig-signed port-st)))
12289+
(not (assoc port (verilog-decls-get-signals moddecls)))
12290+
(not (equal (verilog-sig-bits port-st)
12291+
(verilog-sig-bits (assoc port (verilog-decls-get-signals moddecls))))))
12292+
vl-bits
12293+
""))
1229312294
;; Default net value if not found
12294-
(setq dflt-bits (if (or (and (verilog-sig-bits port-st)
12295+
(setq
12296+
dflt-bits (if (or (and (verilog-sig-bits port-st)
1229512297
(verilog-sig-multidim port-st))
1229612298
(verilog-sig-memory port-st))
1229712299
(concat "/*" vl-mbits vl-bits
1229812300
;; .[ used to separate packed from unpacked
1229912301
(if vl-memory "." "")
1230012302
(if vl-memory vl-memory "")
1230112303
"*/")
12302-
(concat vl-bits))
12304+
(concat auto-inst-vector))
1230312305
tpl-net (concat port
1230412306
(if (and vl-modport
1230512307
;; .modport cannot be added if attachment is
@@ -12338,10 +12340,20 @@ If PAR-VALUES replace final strings with these parameter values."
1233812340
(if (numberp value) (setq value (number-to-string value)))
1233912341
value))
1234012342
(substring tpl-net (match-end 0))))))
12343+
;; Get range based off template net
12344+
(setq auto-inst-vector-tpl
12345+
(if (or (eq verilog-auto-inst-vector t)
12346+
(and (eq verilog-auto-inst-vector `unsigned)
12347+
(not (verilog-sig-signed port-st)))
12348+
(not (assoc tpl-net (verilog-decls-get-signals moddecls)))
12349+
(not (equal (verilog-sig-bits port-st)
12350+
(verilog-sig-bits (assoc tpl-net (verilog-decls-get-signals moddecls))))))
12351+
vl-bits
12352+
""))
1234112353
;; Replace @ and [] magic variables in final output
1234212354
(setq tpl-net (verilog-string-replace-matches "@" tpl-num nil nil tpl-net))
1234312355
(setq tpl-net (verilog-string-replace-matches "\\[\\]\\[\\]" dflt-bits nil nil tpl-net))
12344-
(setq tpl-net (verilog-string-replace-matches "\\[\\]" vl-bits nil nil tpl-net)))
12356+
(setq tpl-net (verilog-string-replace-matches "\\[\\]" auto-inst-vector-tpl nil nil tpl-net)))
1234512357
;; Insert it
1234612358
(when (or tpl-ass (not verilog-auto-inst-template-required))
1234712359
(verilog--auto-inst-first indent-pt section)

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