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amd : ACP_7_0 : Add SW topology for the platform ACP_7_0.
amd : ACP_7_0 : Add SW topology for the platform ACP_7_0. Signed-off-by: SaiSurya Ch <[email protected]>
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tools/topology/topology1/CMakeLists.txt

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@@ -115,6 +115,7 @@ set(TPLGS
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"sof-acp_6_3\;sof-acp_6_3"
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"sof-acp_6_3_sdw\;sof-acp_6_3-rt711-l0-rt1316-l0-rt714-l1"
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"sof-acp_7_0\;sof-acp_7_0"
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"sof-acp_7_0_sdw\;sof-acp_7_0-rt722-l0"
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)
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# This empty 'production/' source subdirectory exists only to create the
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#Required Topology for rt722 with ACP DMIC Card for ACP_7_0
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#
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# PCM Description DAI LINK DAI BE
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# 0       HS Playback 0 SDW0-PIN0-Playback-SimpleJack       AUDIO_TX
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# 1       HS Capture 1 SDW0-PIN3-Capture-SimpleJack    AUDIO_RX
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# 2       Speaker playback 2 SDW0-PIN1-Playback-SmartAmp    BT_TX
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# 4       SDW DMIC 4 SDW0-PIN5-Capture-SmartMic    HS_RX
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#
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# Define the pipelines
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#
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# PCM0 ----> buffer ----> AUDIO_TX
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# PCM1 <---- buffer <---- AUDIO_RX
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# PCM2 ----> buffer ----> BT_TX
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# PCM4 <---- buffer <---- HS_RX
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# Include topology builder
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include(`utils.m4')
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include(`dai.m4')
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include(`pipeline.m4')
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include(`acp-sdw.m4')
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include(`acp-dmic.m4')
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# Include TLV library
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include(`common/tlv.m4')
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# Include Token library
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include(`sof/tokens.m4')
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# Include ACP DSP configuration
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include(`platform/amd/acp.m4')
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DEBUG_START
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#/**********************************************************************************/
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# PCM 0, HS Playback, DAI link id 0, Dai index 0(Audio_Tx), BE SW0-PIN0-PLAYBACK
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#Driver dai index and dai BE
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#DAI Index(Instance * 64 + base_index) DAI_BE
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#0(AUDIO_TX) SDW0-PIN0-PLAYBACK-SimpleJack
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#1(BT_TX) SDW0-PIN1-PLAYBACK-SmartAmp
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#2(HS_TX) SDW0-PIN2-PLAYBACK
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#3(AUDIO_RX) SDW0-PIN3-CAPTURE-SimpleJack
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#4(BT_RX) SDW0-PIN4-CAPTURE-SmartAmp
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#5(HS_RX) SDW0-PIN5-CAPTURE
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define(DI_SDW0_ACP_SW_Audio_TX, 0)
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define(DI_SDW0_ACP_SW_BT_TX, 1)
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define(DI_SDW0_ACP_SW_HS_TX, 2)
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define(DI_SDW0_ACP_SW_Audio_RX, 3)
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define(DI_SDW0_ACP_SW_BT_RX, 4)
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define(DI_SDW0_ACP_SW_HS_RX, 5)
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define(DI_SDW1_ACP_P1_SW_BT_RX, 68)
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define(DI_SDW1_ACP_P1_SW_BT_TX, 65)
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define(DAI_BE_SDW0_ACP_SW_HS_TX, SDW0-PIN2-PLAYBACK)
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define(DAI_BE_SDW1_ACP_P1_SW_BT_RX, SDW1-PIN1-CAPTURE-SmartMic)
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define(DAI_BE_SDW1_ACP_P1_SW_BT_TX, SDW1-PIN1-PLAYBACK)
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define(DAI_BE_ACP_SW_Audio_RX, SDW0-PIN3-CAPTURE-SimpleJack)
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define(DAI_BE_SDW0_ACP_SW_Audio_TX, SDW0-PIN0-PLAYBACK-SimpleJack)
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define(DAI_BE_SDW0_ACP_SW_BT_RX, SDW0-PIN4-CAPTURE-SmartAmp)
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define(DAI_BE_SDW0_ACP_SW_BT_TX, SDW0-PIN1-PLAYBACK-SmartAmp)
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define(DAI_BE_SDW0_ACP_SW_HS_RX, SDW0-PIN5-CAPTURE-SmartMic)
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#pipeline: name of the predefined pipeline
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#pipe id: pipeline ID. This should be a unique ID identifying the pipeline
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#pcm: PCM ID. This will be used to bind to the correct front end DAI link
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dnl PIPELINE_PCM_ADD(pipeline,
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dnl pipe id, pcm, max channels, format,
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dnl period, priority, core,
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dnl pcm_min_rate, pcm_max_rate, pipeline_rate)
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PIPELINE_PCM_ADD(sof/pipe-passthrough-playback.m4,
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0, 0, 2, s16le,
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2000, 0, 0,
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48000, 48000, 48000)
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dnl DAI_ADD(pipeline,
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dnl pipe id, dai type, dai_index, dai_be,
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dnl buffer, periods, format,
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dnl deadline, priority, core, time_domain)
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DAI_ADD(sof/pipe-dai-playback.m4, 0, ACP_SDW, DI_SDW0_ACP_SW_Audio_TX, DAI_BE_SDW0_ACP_SW_Audio_TX,
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PIPELINE_SOURCE_0, 2, s16le, 2000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA)
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dnl DAI_CONFIG(type, dai_index, link_id, name, acphs_config/acpdmic_config)
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dnl ACPHS_CONFIG(format, mclk, bclk, fsync, tdm, acphs_config_data)
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dnl ACP_CLOCK(clock, freq, codec_provider, polarity)
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dnl ACPHS_CONFIG_DATA(type, idx, valid bits, mclk_id)
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dnl mclk_id is optional
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DAI_CONFIG(ACP_SDW, DI_SDW0_ACP_SW_Audio_TX, 0, DAI_BE_SDW0_ACP_SW_Audio_TX,
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ACP_SDW_CONFIG(ACP_SDW_CONFIG_DATA(ACP_SDW, DI_SDW0_ACP_SW_Audio_TX, 48000, 2)))
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PCM_PLAYBACK_ADD(ACP-SW0-PIN0-Playback-HS, 0, PIPELINE_PCM_0)
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#/**********************************************************************************/
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#/**********************************************************************************/
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#PCM 1, HS Capture, DAI link id 1, Dai index 3(Audio_RX), BE SW0-PIN0-CAPTURE
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# Capture pipeline 1 on PCM 1 using max 2 channels of s16le.
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PIPELINE_PCM_ADD(sof/pipe-passthrough-capture.m4,
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1, 1, 2, s16le,
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2000, 0, 0,
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48000, 48000, 48000)
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# Capture DAI is ACP soundwire using 2 periods
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DAI_ADD(sof/pipe-dai-capture.m4, 1, ACP_SDW, DI_SDW0_ACP_SW_Audio_RX, DAI_BE_ACP_SW_Audio_RX,
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PIPELINE_SINK_1, 2, s16le, 2000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA)
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DAI_CONFIG(ACP_SDW, DI_SDW0_ACP_SW_Audio_RX, 1, DAI_BE_ACP_SW_Audio_RX,
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ACP_SDW_CONFIG(ACP_SDW_CONFIG_DATA(ACP_SDW, DI_SDW0_ACP_SW_Audio_RX, 48000, 2)))
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PCM_CAPTURE_ADD(ACP-SW0-PIN0-Capture-HS, 1, PIPELINE_PCM_1)
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#/**********************************************************************************/
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#/**********************************************************************************/
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#PCM 2, Speaker Playback, DAI link id 2, Dai index 1(BT_TX), BE SW0-PIN1-PLAYBACK
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PIPELINE_PCM_ADD(sof/pipe-passthrough-playback.m4,
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2, 2, 2, s16le,
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2000, 0, 0,
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48000, 48000, 48000)
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# playback DAI is ACP soundwire using 2 periods
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DAI_ADD(sof/pipe-dai-playback.m4, 2, ACP_SDW, DI_SDW0_ACP_SW_BT_TX, DAI_BE_SDW0_ACP_SW_BT_TX,
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PIPELINE_SOURCE_2, 2, s16le, 2000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA)
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DAI_CONFIG(ACP_SDW, DI_SDW0_ACP_SW_BT_TX, 2, DAI_BE_SDW0_ACP_SW_BT_TX,
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ACP_SDW_CONFIG(ACP_SDW_CONFIG_DATA(ACP_SDW, DI_SDW0_ACP_SW_BT_TX, 48000, 2)))
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PCM_PLAYBACK_ADD(ACP-SW0-PIN2-Playback-SPK, 2, PIPELINE_PCM_2)
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#/**********************************************************************************/
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#/**********************************************************************************/
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#PCM 4, SDW Capture, DAI link id 4, Dai index 5(HS_RX), BE SDW0-PIN5-CAPTURE-SmartMic
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# Capture pipeline 1 on PCM 1 using max 2 channels of s16le.
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PIPELINE_PCM_ADD(sof/pipe-passthrough-capture.m4,
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4, 4, 2, s16le,
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2000, 0, 0,
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48000, 48000, 48000)
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# Capture DAI is ACP soundwire using 2 periods
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DAI_ADD(sof/pipe-dai-capture.m4, 4, ACP_SDW, DI_SDW0_ACP_SW_HS_RX, DAI_BE_SDW0_ACP_SW_HS_RX,
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PIPELINE_SINK_4, 2, s16le, 2000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA)
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DAI_CONFIG(ACP_SDW, DI_SDW0_ACP_SW_HS_RX, 4, DAI_BE_SDW0_ACP_SW_HS_RX,
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ACP_SDW_CONFIG(ACP_SDW_CONFIG_DATA(ACP_SDW, DI_SDW0_ACP_SW_HS_RX, 48000, 2)))
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PCM_CAPTURE_ADD(ACP-SW0-PIN5-CAPTURE-DMIC, 4, PIPELINE_PCM_4)
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#/**********************************************************************************/
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DEBUG_END

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