The goal of this project is to write a PCAP file reader and writer in VHDL. Such a reader and writer is useful for debugging network components in a Hardware Simulation.
This project !ONLY! works in a simulation, such as in ISIM or in Modelsim. It will never ever synthesize !!!
Checkout this project into your HDL Development directory and add all the files to your IDE or simulation environment.
TODO: Write usage instructions
- Fork it!
- Create your feature branch:
git checkout -b my-new-feature - Commit your changes:
git commit -am 'Add some feature' - Push to the branch:
git push origin my-new-feature - Submit a pull request :D
2016-11-14 initial Version uploaded
GPLv2 - look at License.txt