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| 1 | + |
| 2 | +// |
| 3 | +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. |
| 4 | +// |
| 5 | +// This file contains confidential and proprietary information |
| 6 | +// of Xilinx, Inc. and is protected under U.S. and |
| 7 | +// international copyright and other intellectual property |
| 8 | +// laws. |
| 9 | +// |
| 10 | +// DISCLAIMER |
| 11 | +// This disclaimer is not a license and does not grant any |
| 12 | +// rights to the materials distributed herewith. Except as |
| 13 | +// otherwise provided in a valid license issued to you by |
| 14 | +// Xilinx, and to the maximum extent permitted by applicable |
| 15 | +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND |
| 16 | +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES |
| 17 | +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING |
| 18 | +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- |
| 19 | +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and |
| 20 | +// (2) Xilinx shall not be liable (whether in contract or tort, |
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| 22 | +// liability) for any loss or damage of any kind or nature |
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| 25 | +// special, incidental, or consequential loss or damage |
| 26 | +// (including loss of data, profits, goodwill, or any type of |
| 27 | +// loss or damage suffered as a result of any action brought |
| 28 | +// by a third party) even if such damage or loss was |
| 29 | +// reasonably foreseeable or Xilinx had been advised of the |
| 30 | +// possibility of the same. |
| 31 | +// |
| 32 | +// CRITICAL APPLICATIONS |
| 33 | +// Xilinx products are not designed or intended to be fail- |
| 34 | +// safe, or for use in any application requiring fail-safe |
| 35 | +// performance, such as life-support or safety devices or |
| 36 | +// systems, Class III medical devices, nuclear facilities, |
| 37 | +// applications related to the deployment of airbags, or any |
| 38 | +// other applications that could lead to death, personal |
| 39 | +// injury, or severe property or environmental damage |
| 40 | +// (individually and collectively, "Critical |
| 41 | +// Applications"). Customer assumes the sole risk and |
| 42 | +// liability of any use of Xilinx products in Critical |
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| 44 | +// regulations governing limitations on product liability. |
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| 46 | +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS |
| 47 | +// PART OF THIS FILE AT ALL TIMES. |
| 48 | +// |
| 49 | +//---------------------------------------------------------------------------- |
| 50 | +// User entered comments |
| 51 | +//---------------------------------------------------------------------------- |
| 52 | +// None |
| 53 | +// |
| 54 | +//---------------------------------------------------------------------------- |
| 55 | +// Output Output Phase Duty Cycle Pk-to-Pk Phase |
| 56 | +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) |
| 57 | +//---------------------------------------------------------------------------- |
| 58 | +// clk_48mhz____48.000______0.000______50.0______281.382____301.601 |
| 59 | +// |
| 60 | +//---------------------------------------------------------------------------- |
| 61 | +// Input Clock Freq (MHz) Input Jitter (UI) |
| 62 | +//---------------------------------------------------------------------------- |
| 63 | +// __primary_________100.000____________0.010 |
| 64 | + |
| 65 | +// The following must be inserted into your Verilog file for this |
| 66 | +// core to be instantiated. Change the instance name and port connections |
| 67 | +// (in parentheses) to your own signal names. |
| 68 | + |
| 69 | +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG |
| 70 | + |
| 71 | + clk_wiz_0 instance_name |
| 72 | + ( |
| 73 | + // Clock out ports |
| 74 | + .clk_48mhz(clk_48mhz), // output clk_48mhz |
| 75 | + // Clock in ports |
| 76 | + .clk_100mhz(clk_100mhz)); // input clk_100mhz |
| 77 | +// INST_TAG_END ------ End INSTANTIATION Template --------- |
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