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r850.c
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// SPDX-License-Identifier: GPL-2.0-only
/*
* RafaelMicro R850 driver (r850.c)
*
* Copyright (c) 2018-2021 nns779
*/
/* Some features are not implemented. */
#include "print_format.h"
#include "r850.h"
#ifdef __linux__
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/delay.h>
#endif
enum r850_imr_direction {
R850_IMR_DIRECTION_GAIN = 0,
R850_IMR_DIRECTION_PHASE = 1,
};
enum r850_calibration {
R850_CALIBRATION_NONE = 0,
R850_CALIBRATION_IMR,
R850_CALIBRATION_LPF,
};
static const u8 init_regs[R850_NUM_REGS] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0xca, 0xc0, 0x72, 0x50, 0x00, 0xe0, 0x00, 0x30,
0x86, 0xbb, 0xf8, 0xb0, 0xd2, 0x81, 0xcd, 0x46,
0x37, 0x40, 0x89, 0x8c, 0x55, 0x95, 0x07, 0x23,
0x21, 0xf1, 0x4c, 0x5f, 0xc4, 0x20, 0xa9, 0x6c,
0x53, 0xab, 0x5b, 0x46, 0xb3, 0x93, 0x6e, 0x41
};
static const u8 sleep_regs[R850_NUM_REGS] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x33, 0xee, 0xb9, 0xfe, 0x0f, 0xe1, 0x04, 0x30,
0x86, 0xfb, 0xf8, 0xb0, 0xd2, 0x81, 0xcd, 0x46,
0x37, 0x44, 0x89, 0x8c, 0x55, 0x95, 0x07, 0x23,
0x21, 0xf1, 0x4c, 0x5f, 0xc4, 0x20, 0xa9, 0xfc,
0x53, 0xab, 0x0b, 0x46, 0xb3, 0x93, 0x6e, 0x41
};
static const u8 wakeup_regs[R850_NUM_REGS] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0xca, 0xe0, 0xf2, 0x7c, 0xc0, 0xe0, 0x00, 0x30,
0x86, 0xbb, 0xf8, 0xb0, 0xd2, 0x81, 0xcd, 0x46,
0x37, 0x40, 0x89, 0x8c, 0x55, 0x95, 0x07, 0x23,
0x21, 0xf1, 0x4c, 0x5f, 0xc4, 0x20, 0xa9, 0x6c,
0x53, 0xab, 0x5b, 0x46, 0xb3, 0x93, 0x6e, 0x41
};
static const u8 imr_cal_regs[R850_NUM_REGS] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0xc0, 0x49, 0x3a, 0x90, 0x03, 0xc1, 0x61, 0x71,
0x17, 0xf1, 0x18, 0x55, 0x30, 0x20, 0xf3, 0xed,
0x1f, 0x1c, 0x81, 0x13, 0x00, 0x80, 0x0a, 0x07,
0x21, 0x71, 0x54, 0xf1, 0xf2, 0xa9, 0xbb, 0x0b,
0xa3, 0xf6, 0x0b, 0x44, 0x92, 0x17, 0xe6, 0x80
};
static const u8 lpf_cal_regs[R850_NUM_REGS] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0xc0, 0x49, 0x3f, 0x90, 0x13, 0xe1, 0x89, 0x7a,
0x07, 0xf1, 0x9a, 0x50, 0x30, 0x20, 0xe1, 0x00,
0x00, 0x04, 0x81, 0x11, 0xef, 0xee, 0x17, 0x07,
0x31, 0x71, 0x54, 0xb2, 0xee, 0xa9, 0xbb, 0x0b,
0xa3, 0x00, 0x0b, 0x44, 0x92, 0x1f, 0xe6, 0x80
};
struct r850_lpf_params {
u8 code;
u8 bandwidth;
u8 lsb;
};
struct r850_system_params {
enum r850_bandwidth bandwidth;
u32 if_freq;
u32 filt_cal_if;
u8 bw;
u8 filt_ext_ena;
u8 hpf_notch;
u8 hpf_cor;
u8 filt_comp;
u8 img_gain;
u8 agc_clk;
struct r850_lpf_params lpf;
};
static const struct r850_system_params dvb_t_t2_params[2][6] = {
{
{ R850_BANDWIDTH_6M, 4570, 7550, 1, 0, 0, 0x08, 1, 0, 0, { 0x01, 3, 1 } },
{ R850_BANDWIDTH_7M, 4570, 7920, 1, 0, 0, 0x0b, 1, 0, 0, { 0x04, 2, 0 } },
{ R850_BANDWIDTH_8M, 4570, 8450, 0, 0, 0, 0x0c, 1, 0, 0, { 0x01, 2, 0 } },
{ R850_BANDWIDTH_6M, 5000, 7920, 1, 0, 0, 0x06, 1, 0, 0, { 0x06, 2, 1 } },
{ R850_BANDWIDTH_7M, 5000, 8450, 0, 0, 0, 0x09, 1, 0, 0, { 0x00, 2, 1 } },
{ R850_BANDWIDTH_8M, 5000, 8700, 0, 0, 0, 0x0a, 1, 0, 0, { 0x06, 0, 1 } },
},
{
{ R850_BANDWIDTH_6M, 4570, 7550, 1, 0, 0, 0x08, 1, 3, 1, { 0x01, 3, 1 } },
{ R850_BANDWIDTH_7M, 4570, 7920, 1, 0, 0, 0x0b, 1, 3, 1, { 0x04, 2, 0 } },
{ R850_BANDWIDTH_8M, 4570, 8450, 0, 0, 0, 0x0c, 1, 3, 1, { 0x01, 2, 0 } },
{ R850_BANDWIDTH_6M, 5000, 7920, 1, 0, 0, 0x06, 1, 3, 1, { 0x06, 2, 1 } },
{ R850_BANDWIDTH_7M, 5000, 8450, 0, 0, 0, 0x09, 1, 3, 1, { 0x00, 2, 1 } },
{ R850_BANDWIDTH_8M, 5000, 8700, 0, 0, 0, 0x0a, 1, 3, 1, { 0x06, 0, 1 } },
}
};
static const struct r850_system_params dvb_t2_1_params[2][2] = {
{
{ R850_BANDWIDTH_7M, 1900, 7920, 1, 0, 0, 0x08, 1, 0, 0, { 0x04, 2, 0 } },
{ R850_BANDWIDTH_7M, 5000, 6000, 2, 0, 0, 0x01, 1, 0, 0, { 0x0b, 3, 1 } },
},
{
{ R850_BANDWIDTH_7M, 1900, 7920, 1, 0, 0, 0x08, 1, 3, 1, { 0x04, 2, 0 } },
{ R850_BANDWIDTH_7M, 5000, 6000, 2, 0, 0, 0x01, 1, 3, 1, { 0x0b, 3, 1 } },
}
};
static const struct r850_system_params dvb_c_params[2][4] = {
{
{ R850_BANDWIDTH_6M, 5070, 8100, 1, 0, 0, 0x05, 1, 0, 0, { 0x02, 2, 0 } },
{ R850_BANDWIDTH_8M, 5070, 9550, 0, 0, 0, 0x0b, 1, 0, 0, { 0x04, 0, 0 } },
{ R850_BANDWIDTH_6M, 5000, 7780, 1, 0, 0, 0x06, 1, 0, 0, { 0x01, 2, 1 } },
{ R850_BANDWIDTH_8M, 5000, 9250, 0, 0, 0, 0x0b, 1, 0, 0, { 0x05, 0, 1 } },
},
{
{ R850_BANDWIDTH_6M, 5070, 8100, 1, 0, 0, 0x05, 1, 3, 1, { 0x02, 2, 0 } },
{ R850_BANDWIDTH_8M, 5070, 9550, 0, 0, 0, 0x0b, 1, 3, 1, { 0x04, 0, 0 } },
{ R850_BANDWIDTH_6M, 5000, 7780, 1, 0, 0, 0x06, 1, 3, 1, { 0x01, 2, 1 } },
{ R850_BANDWIDTH_8M, 5000, 9250, 0, 0, 0, 0x0b, 1, 3, 1, { 0x05, 0, 1 } },
}
};
static const struct r850_system_params j83b_params[2][2] = {
{
{ R850_BANDWIDTH_6M, 5070, 8100, 1, 0, 0, 0x05, 1, 0, 0, { 0x03, 2, 1 } },
{ R850_BANDWIDTH_6M, 5000, 7550, 1, 0, 0, 0x05, 1, 0, 0, { 0x05, 2, 1 } },
},
{
{ R850_BANDWIDTH_6M, 5070, 8100, 1, 0, 0, 0x05, 1, 3, 1, { 0x03, 2, 1 } },
{ R850_BANDWIDTH_6M, 5000, 7550, 1, 0, 0, 0x05, 1, 3, 1, { 0x05, 2, 1 } },
}
};
static const struct r850_system_params isdb_t_params[2][3] = {
{
{ R850_BANDWIDTH_6M, 4063, 7070, 1, 0, 0, 0x08, 1, 0, 0, { 0x02, 3, 1 } },
{ R850_BANDWIDTH_6M, 4570, 7400, 1, 0, 0, 0x05, 1, 0, 0, { 0x08, 2, 0 } },
{ R850_BANDWIDTH_6M, 5000, 7780, 1, 1, 0, 0x03, 1, 0, 0, { 0x05, 2, 0 } },
},
{
{ R850_BANDWIDTH_6M, 4063, 7070, 1, 0, 0, 0x0a, 1, 3, 1, { 0x02, 3, 1 } },
{ R850_BANDWIDTH_6M, 4570, 7400, 1, 0, 0, 0x08, 1, 3, 1, { 0x08, 2, 0 } },
{ R850_BANDWIDTH_6M, 5000, 7780, 1, 0, 0, 0x03, 1, 3, 1, { 0x05, 2, 0 } },
}
};
static const struct r850_system_params dtmb_params[2][4] = {
{
{ R850_BANDWIDTH_6M, 4500, 7200, 1, 0, 0, 0x08, 1, 0, 0, { 0x02, 3, 1 } },
{ R850_BANDWIDTH_8M, 4570, 8450, 0, 0, 0, 0x0c, 1, 0, 0, { 0x00, 2, 1 } },
{ R850_BANDWIDTH_6M, 5000, 8100, 1, 0, 0, 0x06, 1, 0, 0, { 0x04, 2, 1 } },
{ R850_BANDWIDTH_8M, 5000, 8800, 0, 0, 0, 0x0b, 2, 0, 0, { 0x05, 0, 1 } },
},
{
{ R850_BANDWIDTH_6M, 4500, 7200, 1, 0, 0, 0x08, 1, 3, 1, { 0x02, 3, 1 } },
{ R850_BANDWIDTH_8M, 4570, 8450, 0, 0, 0, 0x0c, 1, 3, 1, { 0x00, 2, 1 } },
{ R850_BANDWIDTH_6M, 5000, 8100, 1, 0, 0, 0x06, 1, 3, 1, { 0x04, 2, 1 } },
{ R850_BANDWIDTH_8M, 5000, 8800, 0, 0, 0, 0x0b, 2, 3, 1, { 0x05, 0, 1 } },
}
};
static const struct r850_system_params atsc_params[2][2] = {
{
{ R850_BANDWIDTH_6M, 5070, 8050, 1, 0, 0, 0x05, 1, 0, 0, { 0x03, 2, 0 } },
{ R850_BANDWIDTH_6M, 5000, 7920, 1, 0, 0, 0x05, 1, 0, 0, { 0x04, 2, 0 } },
},
{
{ R850_BANDWIDTH_6M, 5070, 8050, 1, 0, 0, 0x05, 1, 3, 1, { 0x03, 2, 0 } },
{ R850_BANDWIDTH_6M, 5000, 7920, 1, 0, 0, 0x05, 1, 3, 1, { 0x04, 2, 0 } },
}
};
static const struct r850_system_params *sys_params[10][2] = {
{ NULL, NULL },
{ dvb_t_t2_params[0], dvb_t_t2_params[1] },
{ dvb_t_t2_params[0], dvb_t_t2_params[1] },
{ dvb_t2_1_params[0], dvb_t2_1_params[1] },
{ dvb_c_params[0], dvb_c_params[1] },
{ j83b_params[0], j83b_params[1] },
{ isdb_t_params[0], isdb_t_params[1] },
{ dtmb_params[0], dtmb_params[1] },
{ atsc_params[0], atsc_params[1] },
{ NULL, NULL },
};
static const int sys_param_num[10][2] = {
{ 0, 0 },
{ ARRAY_SIZE(dvb_t_t2_params[0]), ARRAY_SIZE(dvb_t_t2_params[1]) },
{ ARRAY_SIZE(dvb_t_t2_params[0]), ARRAY_SIZE(dvb_t_t2_params[1]) },
{ ARRAY_SIZE(dvb_t2_1_params[0]), ARRAY_SIZE(dvb_t2_1_params[1]) },
{ ARRAY_SIZE(dvb_c_params[0]), ARRAY_SIZE(dvb_c_params[1]) },
{ ARRAY_SIZE(j83b_params[0]), ARRAY_SIZE(j83b_params[1]) },
{ ARRAY_SIZE(isdb_t_params[0]), ARRAY_SIZE(isdb_t_params[1]) },
{ ARRAY_SIZE(dtmb_params[0]), ARRAY_SIZE(dtmb_params[1]) },
{ ARRAY_SIZE(atsc_params[0]), ARRAY_SIZE(atsc_params[1]) },
{ 0, 0 },
};
struct r850_system_frequency_params {
u32 if_freq;
u32 rf_freq_min;
u32 rf_freq_max;
u8 lna_top;
u8 lna_vtl_h;
u8 lna_nrb_det;
u8 lna_rf_dis_mode;
u8 lna_rf_charge_cur;
u8 lna_rf_dis_curr;
u8 lna_dis_slow_fast;
u8 rf_top;
u8 rf_vtl_h;
u8 rf_gain_limit;
u8 rf_dis_slow_fast;
u8 rf_lte_psg;
u8 nrb_top;
u8 nrb_bw_hpf;
u8 nrb_bw_lpf;
u8 mixer_top;
u8 mixer_vth;
u8 mixer_vtl;
u8 mixer_amp_lpf;
u8 mixer_gain_limit;
u8 mixer_detbw_lpf;
u8 mixer_filter_dis;
u8 filter_top;
u8 filter_vth;
u8 filter_vtl;
u8 filt_3th_lpf_cur;
u8 filt_3th_lpf_gain;
u8 bb_dis_curr;
u8 bb_det_mode;
u8 na_pwr_det;
u8 enb_poly_gain;
u8 img_nrb_adder;
u8 hpf_comp;
u8 fb_res_1st;
};
static const struct r850_system_frequency_params dvb_t_t2_freq_params[4] = {
{
0, 0, 340000,
5, 0x5a, 0, 1, 1, 1, 0x05,
4, 0x5a, 0, 0x05, 1,
5, 0, 2,
9, 0x09, 0x04, 4, 3, 0, 2,
4, 0x09, 0x04,
1, 3, 0, 0, 1, 0, 2, 1, 1
},
{
0, 662001, 670000,
4, 0x5a, 0, 4, 1, 1, 0x05,
4, 0x5a, 0, 0x05, 1,
4, 0, 2,
9, 0x09, 0x04, 4, 3, 0, 2,
4, 0x09, 0x04,
1, 3, 0, 0, 1, 0, 2, 1, 1
},
{
0, 782001, 790000,
5, 0x5a, 0, 2, 0, 1, 0x05,
4, 0x5a, 0, 0x05, 1,
4, 0, 2,
9, 0x09, 0x04, 4, 3, 0, 2,
4, 0x09, 0x04,
1, 3, 0, 0, 1, 0, 2, 1, 1
},
{
0, 0, 0,
4, 0x5a, 0, 1, 1, 1, 0x05,
4, 0x5a, 0, 0x05, 1,
4, 0, 2,
9, 0x09, 0x04, 4, 3, 0, 2,
4, 0x09, 0x04,
1, 3, 0, 0, 1, 0, 2, 1, 1
}
};
static const struct r850_system_frequency_params dvb_c_freq_params[2] = {
{
0, 0, 660000,
4, 0x5a, 0, 1, 1, 1, 0x05,
4, 0x4a, 0, 0x05, 0,
5, 0, 2,
12, 0x09, 0x04, 4, 2, 0, 0,
12, 0x09, 0x04,
1, 0, 1, 0, 1, 1, 2, 1, 1
},
{
0, 0, 0,
4, 0x5a, 0, 1, 1, 1, 0x05,
3, 0x4a, 0, 0x05, 0,
5, 0, 2,
12, 0x09, 0x04, 4, 2, 0, 0,
12, 0x09, 0x04,
1, 0, 1, 0, 1, 1, 1, 1, 1
}
};
static const struct r850_system_frequency_params j83b_freq_params[3] = {
{
0, 0, 335000,
5, 0x5a, 0, 1, 1, 1, 0x05,
4, 0x4a, 0, 0x05, 0,
5, 0, 0,
12, 0x09, 0x04, 7, 2, 0, 0,
12, 0x09, 0x04,
1, 0, 1, 0, 1, 1, 2, 1, 1
},
{
0, 340001, 660000,
5, 0x5a, 0, 1, 1, 1, 0x05,
4, 0x4a, 0, 0x05, 0,
5, 0, 0,
12, 0x09, 0x04, 7, 2, 0, 0,
12, 0x09, 0x04,
1, 0, 1, 0, 1, 1, 2, 1, 1
},
{
0, 0, 0,
4, 0x5a, 0, 1, 1, 1, 0x05,
3, 0x4a, 0, 0x05, 0,
5, 0, 0,
12, 0x09, 0x04, 7, 2, 0, 0,
12, 0x09, 0x04,
1, 0, 1, 0, 1, 1, 1, 1, 1
}
};
static const struct r850_system_frequency_params isdb_t_freq_params[10] = {
/* ISDB-T 4063 */
{
4063, 0, 340000,
5, 0x6b, 0, 1, 1, 1, 0x05,
5, 0x4a, 0, 0x05, 1,
12, 0, 2,
15, 0x09, 0x04, 7, 3, 0, 0,
12, 0x09, 0x04,
1, 0, 1, 0, 1, 0, 2, 2, 1
},
{
4063, 470000, 487999,
6, 0x8c, 0, 1, 1, 1, 0x05,
5, 0x6b, 0, 0x05, 1,
3, 0, 2,
14, 0x09, 0x04, 7, 3, 0, 0,
12, 0x09, 0x04,
1, 3, 1, 0, 1, 1, 3, 2, 1
},
{
4063, 680000, 691999,
5, 0x5a, 0, 2, 1, 1, 0x07,
6, 0x6b, 0, 0x04, 1,
3, 0, 2,
14, 0x09, 0x05, 7, 3, 0, 0,
12, 0x09, 0x04,
1, 3, 1, 0, 0, 1, 3, 2, 1
},
{
4063, 692000, 697999,
5, 0x5b, 0, 2, 1, 1, 0x07,
6, 0x6b, 0, 0x04, 1,
10, 0, 3,
12, 0x09, 0x05, 7, 3, 0, 0,
12, 0x09, 0x04,
1, 3, 1, 0, 0, 1, 2, 2, 1
},
{
4063, 0, 0,
5, 0x5a, 0, 1, 1, 1, 0x05,
6, 0x6b, 0, 0x05, 1,
3, 0, 2,
14, 0x09, 0x04, 7, 3, 0, 0,
12, 0x09, 0x04,
1, 3, 1, 0, 1, 1, 3, 2, 1
},
/* ISDB-T other */
{
0, 0, 340000,
5, 0x6b, 0, 1, 1, 1, 0x05,
5, 0x4a, 0, 0x05, 1,
12, 0, 2,
15, 0x0b, 0x06, 7, 3, 0, 0,
12, 0x09, 0x04,
1, 0, 1, 0, 1, 0, 2, 2, 1
},
{
0, 470000, 487999,
5, 0x5a, 0, 2, 1, 1, 0x07,
6, 0x6b, 0, 0x04, 1,
3, 0, 2,
14, 0x09, 0x05, 7, 3, 0, 0,
12, 0x09, 0x04,
1, 3, 1, 0, 0, 1, 3, 2, 1
},
{
0, 680000, 691999,
5, 0x5b, 0, 2, 1, 1, 0x07,
6, 0x6b, 0, 0x04, 1,
10, 0, 3,
12, 0x09, 0x05, 7, 3, 0, 0,
12, 0x09, 0x04,
1, 3, 1, 0, 0, 1, 2, 2, 1
},
{
0, 692000, 697999,
5, 0x5a, 0, 1, 1, 1, 0x05,
6, 0x6b, 0, 0x05, 1,
3, 0, 2,
14, 0x09, 0x04, 7, 3, 0, 0,
12, 0x09, 0x04,
1, 3, 1, 0, 1, 1, 3, 2, 1
},
{
0, 0, 0,
5, 0x5a, 0, 1, 1, 1, 0x05,
6, 0x6b, 0, 0x05, 1,
3, 0, 2,
14, 0x09, 0x04, 7, 3, 0, 0,
12, 0x09, 0x04,
1, 3, 1, 0, 1, 1, 3, 2, 1
}
};
static const struct r850_system_frequency_params dtmb_freq_params[3] = {
{
0, 0, 100000,
4, 0x6b, 0, 1, 1, 1, 0x05,
4, 0x4a, 0, 0x05, 1,
10, 3, 3,
9, 0x09, 0x04, 4, 1, 0, 2,
4, 0x09, 0x04,
0, 0, 0, 0, 1, 0, 1, 0, 0
},
{
0, 0, 340000,
4, 0x6b, 0, 1, 1, 1, 0x05,
4, 0x4a, 0, 0x05, 1,
10, 0, 2,
9, 0x09, 0x04, 4, 1, 0, 2,
4, 0x09, 0x04,
0, 0, 0, 0, 1, 0, 1, 0, 0
},
{
0, 0, 0,
4, 0x5a, 0, 1, 1, 1, 0x05,
4, 0x4a, 0, 0x05, 1,
6, 3, 2,
9, 0x09, 0x04, 4, 1, 0, 2,
4, 0x09, 0x04,
0, 3, 0, 0, 1, 0, 0, 0, 0
}
};
static const struct r850_system_frequency_params atsc_freq_params[2] = {
{
0, 0, 340000,
6, 0x5a, 0, 1, 1, 1, 0x05,
5, 0x6b, 0, 0x05, 1,
12, 2, 2,
12, 0x0b, 0x04, 7, 2, 1, 2,
6, 0x09, 0x04,
1, 0, 0, 0, 1, 0, 1, 2, 1
},
{
0, 0, 0,
6, 0x5a, 0, 1, 1, 1, 0x05,
5, 0x6b, 0, 0x05, 1,
12, 2, 2,
12, 0x0b, 0x04, 7, 2, 1, 2,
6, 0x09, 0x04,
1, 3, 0, 0, 1, 0, 1, 2, 1
}
};
static const struct r850_system_frequency_params *sys_freq_params[10] = {
NULL,
dvb_t_t2_freq_params,
dvb_t_t2_freq_params,
dvb_t_t2_freq_params,
dvb_c_freq_params,
j83b_freq_params,
isdb_t_freq_params,
dtmb_freq_params,
atsc_freq_params,
NULL,
};
static const int sys_freq_param_num[10] = {
0,
ARRAY_SIZE(dvb_t_t2_freq_params),
ARRAY_SIZE(dvb_t_t2_freq_params),
ARRAY_SIZE(dvb_t_t2_freq_params),
ARRAY_SIZE(dvb_c_freq_params),
ARRAY_SIZE(j83b_freq_params),
ARRAY_SIZE(isdb_t_freq_params),
ARRAY_SIZE(dtmb_freq_params),
ARRAY_SIZE(atsc_freq_params),
0,
};
static const u16 lna_acc_gain[32] = {
0, 15, 26, 34, 50, 61, 75, 87,
101, 117, 130, 144, 154, 164, 176, 188,
199, 209, 220, 226, 233, 232, 232, 232,
232, 247, 262, 280, 296, 311, 296, 308
};
static const u16 rf_acc_gain[16] = {
0, 15, 26, 34, 50, 61, 75, 87,
101, 117, 130, 144, 154, 164, 176, 188
};
static const u16 mixer_acc_gain[16] = {
0, 0, 0, 0, 9, 22, 32, 44,
56, 68, 80, 90, 100, 100, 100, 100
};
static u8 reverse_bit(u8 val)
{
u8 t = val;
t = (t & 0x55) << 1 | (t & 0xaa) >> 1;
t = (t & 0x33) << 2 | (t & 0xcc) >> 2;
t = (t & 0x0f) << 4 | (t & 0xf0) >> 4;
return t;
}
static int r850_read_regs(struct r850_tuner *t, u8 reg, u8 *buf, int len)
{
int ret = 0, i;
u8 b[1 + R850_NUM_REGS];
struct i2c_comm_request req[2];
if (!t || !buf || !len)
return -EINVAL;
if (len > (R850_NUM_REGS - reg))
return -EINVAL;
b[0] = 0x00;
req[0].req = I2C_WRITE_REQUEST;
req[0].addr = t->i2c_addr;
req[0].data = b;
req[0].len = 1;
req[1].req = I2C_READ_REQUEST;
req[1].addr = t->i2c_addr;
req[1].data = b;
req[1].len = reg + len;
ret = i2c_comm_master_request(t->i2c, req, 2);
if (ret) {
dev_err(t->dev,
"r850_read_regs: i2c_comm_master_request() failed. (reg: 0x%02x, len: %d, ret: %d)\n",
reg, len, ret);
} else {
for (i = reg; i < (reg + len); i++)
buf[i - reg] = reverse_bit(b[i]);
}
return ret;
}
static int r850_write_regs(struct r850_tuner *t,
u8 reg,
const u8 *buf, int len)
{
int ret = 0;
u8 b[1 + R850_NUM_REGS];
struct i2c_comm_request req[1];
if (!t || !buf || !len)
return -EINVAL;
if (len > (R850_NUM_REGS - reg))
return -EINVAL;
b[0] = reg;
memcpy(&b[1], buf, len);
req[0].req = I2C_WRITE_REQUEST;
req[0].addr = t->i2c_addr;
req[0].data = b;
req[0].len = 1 + len;
ret = i2c_comm_master_request(t->i2c, req, 1);
if (ret)
dev_err(t->dev,
"r850_write_regs: i2c_comm_master_request() failed. (reg: 0x%02x, len: %d, ret: %d)\n",
reg, len, ret);
return ret;
}
static int r850_init_regs(struct r850_tuner *t)
{
memcpy(t->priv.regs, init_regs, sizeof(t->priv.regs));
#if 0
if (t->config.loop_through) {
t->priv.regs[0x08] |= 0xc0;
t->priv.regs[0x0a] |= 0x02;
} else {
t->priv.regs[0x08] &= 0x3f;
t->priv.regs[0x08] |= 0x40;
t->priv.regs[0x0a] &= 0xfd;
}
if (t->config.clock_out)
t->priv.regs[0x22] &= 0xfb;
else
t->priv.regs[0x22] |= 0x04;
#endif
return 0;
}
static int r850_set_xtal_cap(struct r850_tuner *t, u8 cap)
{
u8 c = cap;
bool g = false;
if (c > 0x1f) {
c -= 10;
g = true;
}
t->priv.regs[0x21] = (t->priv.regs[0x21] & 0x07) |
((c << 2) & 0x78) | ((g) ? 0x80 : 0x00);
t->priv.regs[0x22] = (t->priv.regs[0x22] & 0xf7) | ((c << 3) & 0x08);
return 0;
}
static int r850_set_pll(struct r850_tuner *t,
u32 lo_freq, u32 if_freq,
enum r850_system sys)
{
int ret = 0;
u32 xtal, vco_min, vco_max, vco_freq;
u16 nint, vco_fra;
u16 nsdm = 2, sdm = 0;
u8 mix_div = 2, div = 0, ni, si;
u8 xtal_div;
u8 b;
u16 div_judge;
xtal = t->config.xtal;
vco_min = 2200000;
if (!t->priv.chip)
vco_min += 70000;
vco_max = vco_min * 2;
vco_freq = lo_freq * mix_div;
t->priv.regs[0x20] &= 0xfc;
t->priv.regs[0x2e] |= 0x40;
t->priv.regs[0x0c] &= 0x3c;
t->priv.regs[0x09] &= 0xf9;
t->priv.regs[0x22] &= 0x3f;
t->priv.regs[0x0b] &= 0xc3;
t->priv.regs[0x0b] |= 0x10;
t->priv.regs[0x25] &= 0xef;
t->priv.regs[0x25] |= 0x20;
if (lo_freq < 100000) {
if (t->priv.xtal_pwr > 1)
b = 3 - t->priv.xtal_pwr;
else
b = 2;
} else if (lo_freq < 130000) {
if (t->priv.xtal_pwr > 2)
b = 3 - t->priv.xtal_pwr;
else
b = 1;
} else {
b = 0;
}
ret = r850_set_xtal_cap(t, 0x27);
if (ret)
return ret;
t->priv.regs[0x22] &= 0xcf;
t->priv.regs[0x22] |= ((b << 4) & 0x30);
/* xtal == 24000 */
div_judge = ((lo_freq + if_freq) / 1000 / 12);
t->priv.regs[0x1e] &= 0x1f;
t->priv.regs[0x25] &= 0xfd;
switch (div_judge) {
case 4:
case 10:
case 22:
case 24:
case 28:
t->priv.regs[0x25] |= 0x02;
break;
default:
t->priv.regs[0x25] |= 0x00;
break;
}
if (t->priv.chip)
t->priv.regs[0x2f] &= 0xfd;
else
t->priv.regs[0x2f] &= 0xfc;
while (div < 6) {
if (vco_min <= vco_freq && vco_freq < vco_max)
break;
mix_div *= 2;
vco_freq = lo_freq * mix_div;
div++;
}
xtal_div = 0;
t->priv.regs[0x22] &= 0xfc;
if (sys != R850_SYSTEM_UNDEFINED) {
if (lo_freq < 380500) {
if (!(div_judge & 1)) {
xtal /= 2;
t->priv.regs[0x22] |= 0x02;
xtal_div = 1;
}
} else if ((lo_freq + if_freq - 478000) < 4000 &&
sys == R850_SYSTEM_ISDB_T) {
#if 1
xtal /= 4;
t->priv.regs[0x22] |= 0x03;
xtal_div = 3;
#endif
}
}
t->priv.regs[0x0b] &= 0xfe;
t->priv.regs[0x2d] &= 0xf3;
if (mix_div == 8)
t->priv.regs[0x2d] |= 0x04;
else if (mix_div == 16)
t->priv.regs[0x2d] |= 0x08;
else if (mix_div >= 32)
t->priv.regs[0x2d] |= 0x0c;
t->priv.regs[0x2e] &= 0xfc;
t->priv.regs[0x20] &= 0xec;
if (mix_div == 2 || mix_div == 4) {
t->priv.regs[0x2e] |= 0x01;
} else {
t->priv.regs[0x2e] |= 0x02;
t->priv.regs[0x20] |= 0x01;
}
t->priv.regs[0x11] &= 0x7f;
if (mix_div == 8)
t->priv.regs[0x11] |= 0x80;
t->priv.regs[0x1e] &= 0xe3;
t->priv.regs[0x1e] |= ((div << 2) & 0x1c);
nint = (vco_freq / 2) / xtal;
vco_fra = vco_freq - (xtal * 2 * nint);
if (vco_fra < (xtal / 64)) {
vco_fra = 0;
} else if (vco_fra > (xtal * 127 / 64)) {
vco_fra = 0;
nint++;
} else if (vco_fra > (xtal * 127 / 128) && (xtal > vco_fra)) {
vco_fra = xtal * 127 / 128;
} else if ((xtal < vco_fra) && (vco_fra < (xtal * 129 / 128))) {
vco_fra = xtal * 129 / 128;
}
ni = (nint - 13) / 4;
si = nint - 13 - (ni * 4);
t->priv.regs[0x1b] &= 0x80;
t->priv.regs[0x1b] |= (ni & 0x7f);
t->priv.regs[0x1e] &= 0xfc;
t->priv.regs[0x1e] |= (si & 0x03);
t->priv.regs[0x20] &= 0x3f;
while (vco_fra > 1) {
if ((xtal * 2 / nsdm) < vco_fra) {
vco_fra -= (xtal * 2) / nsdm;
sdm += 0x8000 / (nsdm / 2);
if (nsdm & 0x8000)
break;
}
nsdm += nsdm;
}
t->priv.regs[0x1c] = (sdm & 0xff);
t->priv.regs[0x1d] = ((sdm >> 8) & 0xff);
ret = r850_write_regs(t, 0x08, &t->priv.regs[0x08], 0x28);
if (ret)
return ret;
switch (xtal_div) {
case 0:
msleep(10);
break;
case 1:
case 2:
msleep(20);
break;
default:
msleep(40);
break;
}
if (!t->priv.chip)
t->priv.regs[0x2f] &= 0xfc;
t->priv.regs[0x2f] |= 0x02;
return r850_write_regs(t, 0x2f, &t->priv.regs[0x2f], 0x01);
}
static int r850_set_mux(struct r850_tuner *t,
u32 rf_freq, u32 lo_freq,
enum r850_system sys)
{
u8 imr_idx;
u8 imr_gain, imr_phase, imr_iqcap;
u8 rf_poly;
u8 lpf_cap, lpf_notch;
u8 tf_hpf_bpf, tf_hpf_cnr, tf_diplexer;
if (lo_freq < 170000)
imr_idx = 0;
else if (lo_freq < 240000)
imr_idx = 4;
else if (lo_freq < 400000)
imr_idx = 1;
else if (lo_freq < 760000)
imr_idx = 2;
else
imr_idx = 3;
if (lo_freq < 580000)
tf_hpf_bpf = 7;
else if (lo_freq < 660000)
tf_hpf_bpf = 1;
else if (lo_freq < 780000)
tf_hpf_bpf = 6;
else if (lo_freq < 900000)
tf_hpf_bpf = 4;
else
tf_hpf_bpf = 0;
if (lo_freq < 133000)
rf_poly = 2;
else if (lo_freq < 221000)
rf_poly = 1;
else if (lo_freq < 760000)
rf_poly = 0;
else
rf_poly = 3;
if (lo_freq < 480000)
tf_hpf_cnr = 3;
else if (lo_freq < 550000)
tf_hpf_cnr = 2;
else if (lo_freq < 700000)
tf_hpf_cnr = 1;
else
tf_hpf_cnr = 0;
if (sys == R850_SYSTEM_DVB_C || sys == R850_SYSTEM_J83B) {
if (lo_freq < 77000) {
lpf_notch = 10;
lpf_cap = 15;
} else if (lo_freq < 85000) {
lpf_notch = 4;
lpf_cap = 15;
} else if (lo_freq < 115000) {
lpf_notch = 3;
lpf_cap = 13;
} else if (lo_freq < 125000) {
lpf_notch = 1;
lpf_cap = 11;
} else if (lo_freq < 141000) {
lpf_notch = 0;
lpf_cap = 9;
} else if (lo_freq < 157000) {
lpf_notch = 0;
lpf_cap = 8;
} else if (lo_freq < 181000) {
lpf_notch = 0;
lpf_cap = 6;
} else if (lo_freq < 205000) {
lpf_notch = 0;
lpf_cap = 3;
} else {
lpf_notch = 0;
lpf_cap = 0;
}
} else {
if (lo_freq < 73000) {
lpf_notch = 10;
lpf_cap = 8;
} else if (lo_freq < 81000) {
lpf_notch = 4;
lpf_cap = 8;
} else if (lo_freq < 89000) {
lpf_notch = 3;
lpf_cap = 8;
} else if (lo_freq < 121000) {
lpf_notch = 1;
lpf_cap = 6;
} else if (lo_freq < 145000) {
lpf_notch = 0;
lpf_cap = 4;
} else if (lo_freq < 153000) {
lpf_notch = 0;
lpf_cap = 3;
} else if (lo_freq < 177000) {
lpf_notch = 0;
lpf_cap = 2;
} else if (lo_freq < 201000) {
lpf_notch = 0;
lpf_cap = 1;
} else {
lpf_notch = 0;
lpf_cap = 0;
}
}
tf_diplexer = (lo_freq < 330000) ? 2 : 0;
if (t->priv.imr_cal[t->priv.mixer_mode].done &&
t->priv.imr_cal[t->priv.mixer_mode].result[imr_idx]) {
struct r850_imr *imr = &t->priv.imr_cal[t->priv.mixer_mode].imr[imr_idx];
imr_gain = imr->gain;
imr_phase = imr->phase;
imr_iqcap = imr->iqcap;
} else if (sys != R850_SYSTEM_UNDEFINED) {
imr_gain = 0x02;
imr_phase = 0x00;
imr_iqcap = 0x00;
} else {
imr_gain = 0x00;
imr_phase = 0x00;
imr_iqcap = 0x00;
}
t->priv.regs[0x0e] &= 0x03;
t->priv.regs[0x0e] |= ((tf_diplexer << 2) & 0x0c);
t->priv.regs[0x0e] |= ((lpf_cap << 4) & 0xf0);
t->priv.regs[0x0f] &= 0xf0;
t->priv.regs[0x0f] |= (lpf_notch & 0x0f);
t->priv.regs[0x10] &= 0xe0;
t->priv.regs[0x10] |= ((tf_hpf_cnr << 3) & 0x18);
t->priv.regs[0x10] |= (tf_hpf_bpf & 0x07);
t->priv.regs[0x12] &= 0xfc;
t->priv.regs[0x12] |= (rf_poly & 0x03);
t->priv.regs[0x14] &= 0xd0;
t->priv.regs[0x14] |= (imr_gain & 0x2f);
t->priv.regs[0x15] &= 0x10;
t->priv.regs[0x15] |= (imr_phase & 0x2f);