wip lut interface updates

Author: richardyrh

src/main/scala/gemmini/Controller.scala

@@ -214,9 +214,9 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data]
       val scale_mem_write_act = Flipped(Decoupled(new ScalingFactorWriteReq(s)))
       val requant_in_gpu = Flipped(Decoupled(new RequantizerInBundle(q.numGPUInputLanes, q.inputBits)))
       val requant_out = Decoupled(new RequantizerOutBundle(q.numOutputLanes, q.maxOutputBits))
-      val lut0 = Flipped(Decoupled(new QuantLutWriteBundle(l)))
-      val lut1 = Flipped(Decoupled(new QuantLutWriteBundle(l)))
-      val lut2 = Flipped(Decoupled(new QuantLutWriteBundle(l)))
+      val lut0 = Flipped(Decoupled(new QuantLutWriteBundle(l(0))))
+      val lut1 = Flipped(Decoupled(new QuantLutWriteBundle(l(1))))
+      val lut2 = Flipped(Decoupled(new QuantLutWriteBundle(l(2))))
       val scale_factor_out = Decoupled(new ScalingFactorWriteReq(s.ScaleMemWriteAddrWidth, s.ScaleMemWriteAddrWidth))
     })
 

src/main/scala/gemmini/MxConfigFragments.scala

@@ -37,12 +37,17 @@ case class GemminiRequantizerConfig(
 )
 
 case class GemminiLUTConfig(
-  numBits: Int = 96,
-  numEntries: Int = 16,
-  numTables: Int = 3,
+  numBits: Seq[Int] = Seq(96, 96, 96),
+  numEntries: Seq[Int] = Seq(16, 16, 32),
   rdataWidth: Int = 6,
   raddrWidth: Int = 4, 
-)
+) {
+  def apply(table: Int) = {
+    (numEntries(table), numBits(table))
+  }
+
+  def numTables = numBits.length
+}
 
 object RequantizerDataType extends ChiselEnum {
   val FP8, FP6, FP4 = Value
@@ -86,7 +91,7 @@ class RequantizerOutBundle(numLanes: Int, dataWidth: Int = 8) extends Bundle {
 
 class QuantLutWriteBundle(numEntries: Int, numBits: Int) extends Bundle {
   val data = Vec(numEntries, UInt(numBits.W))
-  def this(config: GemminiLUTConfig) = {
-    this(config.numEntries, config.numBits)
+  def this(config: (Int, Int)) = {
+    this(config._1, config._2)
   }
 }

src/main/scala/gemmini/MxRequantizer.scala

@@ -59,9 +59,9 @@ class MxRequantizerIO(
   val requant_data_in_gpu = Flipped(Decoupled(new RequantizerInBundle(config.numGPUInputLanes, inputdataWidth)))
   val scaleMem_write = Decoupled(new ScalingFactorWriteReq(scaleMem_addr_width, scaleMem_data_width)) 
   val requant_data_out = Decoupled(new RequantizerOutBundle(outputnumLanes))
-  val lut0_write = Flipped(Decoupled(new QuantLutWriteBundle(lutConfig)))
-  val lut1_write = Flipped(Decoupled(new QuantLutWriteBundle(lutConfig)))
-  val lut2_write = Flipped(Decoupled(new QuantLutWriteBundle(lutConfig)))
+  val lut0_write = Flipped(Decoupled(new QuantLutWriteBundle(lutConfig(0))))
+  val lut1_write = Flipped(Decoupled(new QuantLutWriteBundle(lutConfig(1))))
+  val lut2_write = Flipped(Decoupled(new QuantLutWriteBundle(lutConfig(2))))
   val spad_projected_data = Vec(sp_banks, Flipped(new ScratchpadReadIO(sp_bank_entries, sp_width_projected)))
   val spad_deprojected_data = Vec(sp_banks, new ScratchpadReadIO(sp_bank_entries, sp_width))
   val fp8_mode = Input(Bool())  // true for 64-lane mode, false for 16-lane mode

src/main/scala/gemmini/QuantLut.scala

@@ -16,9 +16,9 @@ class QuantLutIO(
   sp_width_projected: Int,
   iterator_bitwidth: Int,
 ) extends Bundle {
-  val lut_write_weight =  Flipped(Decoupled(new QuantLutWriteBundle(lutConfig))) //input
-  val lut_write_act_in =  Flipped(Decoupled(new QuantLutWriteBundle(lutConfig))) //input
-  val lut_write_act_out =  Flipped(Decoupled(new QuantLutWriteBundle(lutConfig))) //input
+  val lut_write_weight =  Flipped(Decoupled(new QuantLutWriteBundle(lutConfig(0)))) //input
+  val lut_write_act_in =  Flipped(Decoupled(new QuantLutWriteBundle(lutConfig(1)))) //input
+  val lut_write_act_out =  Flipped(Decoupled(new QuantLutWriteBundle(lutConfig(2)))) //input
   val quant_fp6 = Flipped(Valid(Vec(outputnumLanes, UInt(lutConfig.rdataWidth.W)))) //input
   val projected_data = Valid(Vec(outputnumLanes, UInt(lutConfig.raddrWidth.W))) //output
   val spad_projected_data   = Vec(sp_banks, new ScratchpadReadIO(sp_bank_entries, sp_width_projected))