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Amanda ShiAmanda Shi
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test lut mmio
1 parent f678ab7 commit 8026a5e

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3 files changed

+19
-13
lines changed

3 files changed

+19
-13
lines changed

src/main/scala/gemmini/Controller.scala

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -257,11 +257,11 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data]
257257
mx_sel(bank) := (ex_controller.io.output_MxFormat === 1.U)
258258
}
259259
}
260-
if(outer.config.lut.isDefined){
261-
mx_requantizer.get.io.lut0_write := DontCare
262-
mx_requantizer.get.io.lut1_write := DontCare
263-
mx_requantizer.get.io.lut2_write := DontCare
264-
}
260+
// if(outer.config.lut.isDefined){
261+
// mx_requantizer.get.io.lut0_write := DontCare
262+
// mx_requantizer.get.io.lut1_write := DontCare
263+
// mx_requantizer.get.io.lut2_write := DontCare
264+
// }
265265
}
266266

267267
/*

src/main/scala/gemmini/MxConfigFragments.scala

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -29,14 +29,14 @@ case class GemminiRequantizerConfig(
2929
minOutputBits: Int = 4,
3030
maxOutputBits: Int = 8,
3131
outputIdBits: Int = 3,
32-
lutUpdateRegularityW : Int = 128,
32+
lutUpdateRegularityW : Int = 128, // means how many elements update once the lut
3333
lutUpdateRegularityActIn : Int = 128,
3434
lutUpdateRegularityActOut : Int = 128,
3535
)
3636

3737
case class GemminiLUTConfig(
3838
numBits: Int = 96,
39-
numEntries: Int = 32,
39+
numEntries: Int = 1,
4040
numTables: Int = 3,
4141
rdataWidth: Int = 6,
4242
raddrWidth: Int = 4,

src/main/scala/gemmini/QuantLut.scala

Lines changed: 12 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -62,15 +62,17 @@ class QuantLut(
6262
when(lutCache_act_in_flag === false.B){
6363
for (lane <- 0 until 32) {
6464
for (entry <- 0 until 16) {
65-
lutCache_act_in_0(lane)(entry) := io.lut_write_act_in.bits.data(lane)((entry+1)*rdataWidth-1, entry*rdataWidth)
65+
//lutCache_act_in_0(lane)(entry) := io.lut_write_act_in.bits.data(lane)((entry+1)*rdataWidth-1, entry*rdataWidth)
66+
lutCache_act_in_0(lane)(entry) := io.lut_write_act_in.bits.data(0)((entry+1)*rdataWidth-1, entry*rdataWidth)
6667
}
6768
lutCache_act_in_flag := ~lutCache_act_in_flag
6869
lutCache_act_in_buffer_0_read_enable := true.B
6970
}
7071
}.otherwise {
7172
for (lane <- 0 until 32) {
7273
for (entry <- 0 until 16) {
73-
lutCache_act_in_1(lane)(entry) := io.lut_write_act_in.bits.data(lane)((entry+1)*rdataWidth-1, entry*rdataWidth)
74+
//lutCache_act_in_1(lane)(entry) := io.lut_write_act_in.bits.data(lane)((entry+1)*rdataWidth-1, entry*rdataWidth)
75+
lutCache_act_in_1(lane)(entry) := io.lut_write_act_in.bits.data(0)((entry+1)*rdataWidth-1, entry*rdataWidth)
7476
}
7577
lutCache_act_in_flag := ~lutCache_act_in_flag
7678
lutCache_act_in_buffer_1_read_enable := true.B
@@ -109,15 +111,17 @@ class QuantLut(
109111
when(lutCache_weight_flag === false.B){
110112
for (lane <- 0 until 32) {
111113
for (entry <- 0 until 16) {
112-
lutCache_weight_0(lane)(entry) := io.lut_write_weight.bits.data(lane)((entry+1)*rdataWidth-1, entry*rdataWidth)
114+
//lutCache_weight_0(lane)(entry) := io.lut_write_weight.bits.data(lane)((entry+1)*rdataWidth-1, entry*rdataWidth)
115+
lutCache_weight_0(lane)(entry) := io.lut_write_weight.bits.data(0)((entry+1)*rdataWidth-1, entry*rdataWidth)
113116
}
114117
}
115118
lutCache_weight_flag := ~lutCache_weight_flag
116119
lutCache_weight_buffer_0_read_enable := true.B
117120
}.otherwise {
118121
for (lane <- 0 until 32) {
119122
for (entry <- 0 until 16) {
120-
lutCache_weight_1(lane)(entry) := io.lut_write_weight.bits.data(lane)((entry+1)*rdataWidth-1, entry*rdataWidth)
123+
//lutCache_weight_1(lane)(entry) := io.lut_write_weight.bits.data(lane)((entry+1)*rdataWidth-1, entry*rdataWidth)
124+
lutCache_weight_1(lane)(entry) := io.lut_write_weight.bits.data(0)((entry+1)*rdataWidth-1, entry*rdataWidth)
121125
}
122126
}
123127
lutCache_weight_flag := ~lutCache_weight_flag
@@ -155,15 +159,17 @@ class QuantLut(
155159
when(lutCache_act_out_flag === false.B){
156160
for (lane <- 0 until 32) {
157161
for (entry <- 0 until 16) {
158-
lutCache_act_out_0(lane)(entry) := io.lut_write_act_out.bits.data(lane)((entry+1)*rdataWidth-1, entry*rdataWidth)
162+
//lutCache_act_out_0(lane)(entry) := io.lut_write_act_out.bits.data(lane)((entry+1)*rdataWidth-1, entry*rdataWidth)
163+
lutCache_act_out_0(lane)(entry) := io.lut_write_act_out.bits.data(0)((entry+1)*rdataWidth-1, entry*rdataWidth)
159164
}
160165
}
161166
lutCache_act_out_flag := ~lutCache_act_out_flag
162167
lutCache_act_out_buffer_0_read_enable := true.B
163168
}.otherwise {
164169
for (lane <- 0 until 32) {
165170
for (entry <- 0 until 16) {
166-
lutCache_act_out_1(lane)(entry) := io.lut_write_act_out.bits.data(lane)((entry+1)*rdataWidth-1, entry*rdataWidth)
171+
//lutCache_act_out_1(lane)(entry) := io.lut_write_act_out.bits.data(lane)((entry+1)*rdataWidth-1, entry*rdataWidth)
172+
lutCache_act_out_1(lane)(entry) := io.lut_write_act_out.bits.data(0)((entry+1)*rdataWidth-1, entry*rdataWidth)
167173
}
168174
}
169175
lutCache_act_out_flag := ~lutCache_act_out_flag

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