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Fix missing connections with DontCares
1 parent ff55883 commit 8c8b38b

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3 files changed

+8
-2
lines changed

3 files changed

+8
-2
lines changed

src/main/scala/gemmini/DMA.scala

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -108,6 +108,7 @@ class StreamReader[T <: Data, U <: Data, V <: Data](config: GemminiArrayConfig[T
108108
io.resp.bits.bytes_read := RegEnable(xactTracker.io.peek.entry.bytes_to_read, beatPacker.io.req.fire)
109109
io.resp.bits.last := beatPacker.io.out.bits.last
110110

111+
io.counter := DontCare
111112
io.counter.collect(core.module.io.counter)
112113
io.counter.collect(xactTracker.io.counter)
113114
}
@@ -231,6 +232,7 @@ class StreamReaderCore[T <: Data, U <: Data, V <: Data](config: GemminiArrayConf
231232
tlb_q.io.enq <> tlb_arb.io.out
232233

233234
io.tlb.req.valid := tlb_q.io.deq.valid
235+
io.tlb.req.bits := DontCare
234236
io.tlb.req.bits.tlb_req.vaddr := tlb_q.io.deq.bits.vaddr
235237
io.tlb.req.bits.tlb_req.passthrough := false.B
236238
io.tlb.req.bits.tlb_req.size := 0.U // send_size
@@ -305,6 +307,7 @@ class StreamReaderCore[T <: Data, U <: Data, V <: Data](config: GemminiArrayConf
305307
}
306308

307309
// Performance counter
310+
io.counter := DontCare
308311
CounterEventIO.init(io.counter)
309312
io.counter.connectEventSignal(CounterEvent.RDMA_ACTIVE_CYCLE, state =/= s_idle)
310313
io.counter.connectEventSignal(CounterEvent.RDMA_TLB_WAIT_CYCLES, io.tlb.resp.miss)
@@ -522,6 +525,7 @@ class StreamWriter[T <: Data: Arithmetic](nXacts: Int, beatBits: Int, maxBytes:
522525
tlb_q.io.enq <> tlb_arb.io.out
523526

524527
io.tlb.req.valid := tlb_q.io.deq.fire
528+
io.tlb.req.bits := DontCare
525529
io.tlb.req.bits.tlb_req.vaddr := tlb_q.io.deq.bits.vaddr
526530
io.tlb.req.bits.tlb_req.passthrough := false.B
527531
io.tlb.req.bits.tlb_req.size := 0.U // send_size

src/main/scala/gemmini/FrontendTLB.scala

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -30,15 +30,15 @@ class DecoupledTLB(entries: Int, maxSize: Int, use_firesim_simulation_counters:
3030
extends CoreModule {
3131

3232
val lgMaxSize = log2Ceil(maxSize)
33-
val io = new Bundle {
33+
val io = IO(new Bundle {
3434
val req = Flipped(Valid(new DecoupledTLBReq(lgMaxSize)))
3535
val resp = new TLBResp
3636
val ptw = new TLBPTWIO
3737

3838
val exp = new TLBExceptionIO
3939

4040
val counter = new CounterEventIO()
41-
}
41+
})
4242

4343
val interrupt = RegInit(false.B)
4444
io.exp.interrupt := interrupt
@@ -156,6 +156,7 @@ class FrontendTLB(nClients: Int, entries: Int, maxSize: Int, use_tlb_register_fi
156156

157157
// TODO Return the sum of the TLB counters, rather than just the counters of the first TLB. This only matters if we're
158158
// not using the shared TLB
159+
io.counter := DontCare
159160
tlbs.foreach(_.io.counter.external_reset := false.B)
160161
io.counter.collect(tlbs.head.io.counter)
161162
}

src/main/scala/gemmini/Scratchpad.scala

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -825,6 +825,7 @@ class Scratchpad[T <: Data, U <: Data, V <: Data](config: GemminiArrayConfig[T,
825825
}
826826

827827
// Counter connection
828+
io.counter := DontCare
828829
io.counter.collect(reader.module.io.counter)
829830
io.counter.collect(writer.module.io.counter)
830831
}

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