@@ -108,6 +108,7 @@ class StreamReader[T <: Data, U <: Data, V <: Data](config: GemminiArrayConfig[T
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io.resp.bits.bytes_read := RegEnable (xactTracker.io.peek.entry.bytes_to_read, beatPacker.io.req.fire)
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io.resp.bits.last := beatPacker.io.out.bits.last
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+ io.counter := DontCare
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io.counter.collect(core.module.io.counter)
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io.counter.collect(xactTracker.io.counter)
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}
@@ -231,6 +232,7 @@ class StreamReaderCore[T <: Data, U <: Data, V <: Data](config: GemminiArrayConf
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tlb_q.io.enq <> tlb_arb.io.out
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io.tlb.req.valid := tlb_q.io.deq.valid
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+ io.tlb.req.bits := DontCare
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io.tlb.req.bits.tlb_req.vaddr := tlb_q.io.deq.bits.vaddr
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io.tlb.req.bits.tlb_req.passthrough := false .B
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io.tlb.req.bits.tlb_req.size := 0 .U // send_size
@@ -305,6 +307,7 @@ class StreamReaderCore[T <: Data, U <: Data, V <: Data](config: GemminiArrayConf
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}
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// Performance counter
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+ io.counter := DontCare
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CounterEventIO .init(io.counter)
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io.counter.connectEventSignal(CounterEvent .RDMA_ACTIVE_CYCLE , state =/= s_idle)
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io.counter.connectEventSignal(CounterEvent .RDMA_TLB_WAIT_CYCLES , io.tlb.resp.miss)
@@ -522,6 +525,7 @@ class StreamWriter[T <: Data: Arithmetic](nXacts: Int, beatBits: Int, maxBytes:
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tlb_q.io.enq <> tlb_arb.io.out
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io.tlb.req.valid := tlb_q.io.deq.fire
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+ io.tlb.req.bits := DontCare
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io.tlb.req.bits.tlb_req.vaddr := tlb_q.io.deq.bits.vaddr
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io.tlb.req.bits.tlb_req.passthrough := false .B
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io.tlb.req.bits.tlb_req.size := 0 .U // send_size
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