@@ -108,6 +108,7 @@ class StreamReader[T <: Data, U <: Data, V <: Data](config: GemminiArrayConfig[T
108108 io.resp.bits.bytes_read := RegEnable (xactTracker.io.peek.entry.bytes_to_read, beatPacker.io.req.fire)
109109 io.resp.bits.last := beatPacker.io.out.bits.last
110110
111+ io.counter := DontCare
111112 io.counter.collect(core.module.io.counter)
112113 io.counter.collect(xactTracker.io.counter)
113114 }
@@ -231,6 +232,7 @@ class StreamReaderCore[T <: Data, U <: Data, V <: Data](config: GemminiArrayConf
231232 tlb_q.io.enq <> tlb_arb.io.out
232233
233234 io.tlb.req.valid := tlb_q.io.deq.valid
235+ io.tlb.req.bits := DontCare
234236 io.tlb.req.bits.tlb_req.vaddr := tlb_q.io.deq.bits.vaddr
235237 io.tlb.req.bits.tlb_req.passthrough := false .B
236238 io.tlb.req.bits.tlb_req.size := 0 .U // send_size
@@ -305,6 +307,7 @@ class StreamReaderCore[T <: Data, U <: Data, V <: Data](config: GemminiArrayConf
305307 }
306308
307309 // Performance counter
310+ io.counter := DontCare
308311 CounterEventIO .init(io.counter)
309312 io.counter.connectEventSignal(CounterEvent .RDMA_ACTIVE_CYCLE , state =/= s_idle)
310313 io.counter.connectEventSignal(CounterEvent .RDMA_TLB_WAIT_CYCLES , io.tlb.resp.miss)
@@ -522,6 +525,7 @@ class StreamWriter[T <: Data: Arithmetic](nXacts: Int, beatBits: Int, maxBytes:
522525 tlb_q.io.enq <> tlb_arb.io.out
523526
524527 io.tlb.req.valid := tlb_q.io.deq.fire
528+ io.tlb.req.bits := DontCare
525529 io.tlb.req.bits.tlb_req.vaddr := tlb_q.io.deq.bits.vaddr
526530 io.tlb.req.bits.tlb_req.passthrough := false .B
527531 io.tlb.req.bits.tlb_req.size := 0 .U // send_size
0 commit comments