change scale mem write addr width

Author: Amanda Shi

src/main/scala/gemmini/ExecuteController.scala

@@ -52,7 +52,7 @@ class ExecuteController[T <: Data, U <: Data, V <: Data](xLen: Int, tagWidth: In
     val counter = new CounterEventIO()
     val b_fire = Output(Bool())
     val a_fire = Output(Bool())
-    val scale_mem_mvout_base_addr_act = Output(UInt(32.W))
+    val scale_mem_mvout_base_addr_act = Output(UInt(scale_mem.get.ScaleMemWriteAddrWidth.W))
     val scaleMemCntl = Output(new ScalingFactorCntl(meshRows*tileRows))
   })
 
@@ -124,13 +124,13 @@ class ExecuteController[T <: Data, U <: Data, V <: Data](xLen: Int, tagWidth: In
 
   val scale_mem_mvin_base_addr_act = RegInit(0.U(32.W))
   val scale_mem_mvin_base_addr_w = RegInit(0.U(32.W))
-  val scale_mem_mvout_base_addr_act = RegInit(0.U(32.W))
+  val scale_mem_mvout_base_addr_act = RegInit(0.U(scale_mem.get.ScaleMemWriteAddrWidth.W))
 
   when(functs(0) === CONFIG_SCALE_MEM) {
     val direction = rs2s(0)(63) 
     when(direction === 1.U) { // mvin
       scale_mem_mvin_base_addr_act := rs1s(0)
-      scale_mem_mvin_base_addr_w := rs1s(0) + (config.scale_mem.get.sizeInBytes >> 1).U
+      scale_mem_mvin_base_addr_w := rs1s(0) + (scale_mem.get.sizeInBytes >> 1).U
     }.elsewhen(direction === 0.U) { // mvout
       scale_mem_mvout_base_addr_act := rs1s(0)
     }

src/main/scala/gemmini/GemminiISA.scala

@@ -66,7 +66,7 @@ object GemminiISA {
   //==========================================================================
   val GARBAGE_ADDR      = "hffffffff".U(32.W)
 
-  val CONFIG_SCALE_MEM_RS1_ADDR_WIDTH = 32
+  val CONFIG_SCALE_MEM_RS1_ADDR_WIDTH = 33
   val CONFIG_SCALE_MEM_SPACER_WIDTH = 64 - 1 - CONFIG_SCALE_MEM_RS1_ADDR_WIDTH 
 
   class ConfigScaleMemRs1 extends Bundle {

src/main/scala/gemmini/MxConfigFragments.scala

@@ -11,7 +11,7 @@ case class GemminiScalingFactorMemConfig(
   gpuInputWidthBytes: Int = 8,
   numBanks: Int = 8,
   ScaleMemWriteDataWidth: Int = 256,
-  ScaleMemWriteAddrWidth: Int = 32,
+  ScaleMemWriteAddrWidth: Int = 33,
 ) {
   def depth: Int = (sizeInBytes / (subbankLineSizeInBytes) / numBanks).toInt
   def bankWidthBytes = subbankLineSizeInBytes * subbanksPerBank

src/main/scala/gemmini/MxRequantizer.scala

@@ -67,7 +67,7 @@ class MxRequantizerIO(
   val fp8_mode = Input(Bool())  // true for 64-lane mode, false for 16-lane mode
   val a_fire = Input(Bool())  // from execute controller
   val b_fire = Input(Bool())  // from execute controller
-  val scale_mem_mvout_base_addr_act = Input(UInt(32.W)) // from execute controller
+  val scale_mem_mvout_base_addr_act = Input(UInt(scaleMem_addr_width.W)) // from execute controller
   val counter_i = Input(UInt(iterator_bitwidth.W)) // from  controller
   val counter_j = Input(UInt(iterator_bitwidth.W)) // from  controller
   val counter_k = Input(UInt(iterator_bitwidth.W)) // from  controller
@@ -346,7 +346,7 @@ class MxRequantizer[T <: Data: Arithmetic](
 
   when(scale_buffer_full) {
     io.scaleMem_write.valid := true.B
-    io.scaleMem_write.bits.addr := scale_mem_mvout_base_addr_act + (scale_write_addr_counter << 5) //byte address, scale 32B per write
+    io.scaleMem_write.bits.addr := scale_mem_mvout_base_addr_act + (scale_write_addr_counter << (log2Ceil(scaleMem_data_width/8))) //byte address, scale 32B per write
     io.scaleMem_write.bits.data := Cat(scale_buffer.reverse)
   }
 }