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add 2 more lut writes
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2 files changed

+9
-6
lines changed

2 files changed

+9
-6
lines changed

src/main/scala/gemmini/Controller.scala

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -216,10 +216,9 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data]
216216
mx_io.scale_mem <> spad.module.io.scale_mem.get
217217

218218
mx_io.requant_out <> mx_requantizer.get.io.requant_data_out
219-
// TODO TODO TODO TODO TODO TODO lut1 and lut2
220-
mx_requantizer.get.io.lut_write <> mx_io.lut0
221-
mx_io.lut1.ready := false.B
222-
mx_io.lut2.ready := false.B
219+
mx_requantizer.get.io.lut0_write <> mx_io.lut0
220+
mx_requantizer.get.io.lut1_write <> mx_io.lut1
221+
mx_requantizer.get.io.lut2_write <> mx_io.lut2
223222

224223
Seq(mx_io.requant_in_gpu, mx_io.requant_out, mx_io.lut0, mx_io.lut1, mx_io.lut2).foreach(dontTouch(_))
225224
//Seq( mx_io.requant_out).foreach(dontTouch(_))

src/main/scala/gemmini/MxRequantizer.scala

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,9 @@ class MxRequantizerIO(
5757
val requant_data_in = Flipped(Decoupled(new RequantizerInBundle(inputnumLanes, inputdataWidth)))
5858
val scaleMem_write = Decoupled(new ScalingFactorWriteReq(scaleMem_addr_width, scaleMem_data_width))
5959
val requant_data_out = Decoupled(new RequantizerOutBundle(outputnumLanes))
60-
val lut_write = Flipped(Decoupled(new QuantLutWriteBundle(lutConfig)))
60+
val lut0_write = Flipped(Decoupled(new QuantLutWriteBundle(lutConfig)))
61+
val lut1_write = Flipped(Decoupled(new QuantLutWriteBundle(lutConfig)))
62+
val lut2_write = Flipped(Decoupled(new QuantLutWriteBundle(lutConfig)))
6163
val spad_projected_data = Vec(sp_banks, new ScratchpadReadIO(sp_bank_entries, sp_width_projected))
6264
val spad_deprojected_data = Vec(sp_banks, Flipped(new ScratchpadReadIO(sp_bank_entries, sp_width)))
6365
val fp8_mode = Input(Bool()) // true for 64-lane mode, false for 16-lane mode
@@ -271,7 +273,9 @@ class MxRequantizer[T <: Data: Arithmetic](
271273
// quantLut.io.lut_write.ready := false.B
272274
// }
273275

274-
quantLut.io.lut_write <> io.lut_write
276+
quantLut.io.lut_write <> io.lut0_write
277+
io.lut1_write.ready := false.B
278+
io.lut2_write.ready := false.B
275279

276280
when(quantize_valid && (total_bits_per_element === 6.U)) {
277281
quantLut.io.quant_fp6.valid := true.B

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