scale mem mmio debug

Author: Amanda Shi

src/main/scala/gemmini/AccumulatorMem.scala

@@ -47,7 +47,7 @@ class AccumulatorWriteReq[T <: Data: Arithmetic](n: Int, t: Vec[Vec[T]]) extends
 
 
 class AccumulatorMemIO [T <: Data: Arithmetic, U <: Data](n: Int, t: Vec[Vec[T]], scale_t: U,
-  acc_sub_banks: Int, use_shared_ext_mem: Boolean, use_mx_scaling: Boolean, meshRows: Int, tileRows: Int, sramLineSizeInBytes: Int
+  acc_sub_banks: Int, use_shared_ext_mem: Boolean, use_mx_scaling: Boolean, meshRows: Int, tileRows: Int, bankWidthBits: Int
 ) extends Bundle {
   val read = Flipped(new AccumulatorReadIO(n, t, scale_t))
   val write = Flipped(Decoupled(new AccumulatorWriteReq(n, t)))
@@ -66,10 +66,10 @@ class AccumulatorMemIO [T <: Data: Arithmetic, U <: Data](n: Int, t: Vec[Vec[T]]
 
   val dataType = Input(UInt(2.W)) //this is the input mxformat datatype
   val scale_mem_write_act = if (use_mx_scaling) {
-    Some(Flipped(Decoupled(new ScalingFactorWriteReq(9, 256))))
+    Some(Flipped(Decoupled(new ScalingFactorWriteReq(9, bankWidthBits))))
   } else None
   val scale_mem_write_w = if (use_mx_scaling) {
-    Some(Flipped(Decoupled(new ScalingFactorWriteReq(9, 256))))
+    Some(Flipped(Decoupled(new ScalingFactorWriteReq(9, bankWidthBits))))
   } else None
   val scaleMemCntl = if (use_mx_scaling) {
     Some(Input(new ScalingFactorCntl(meshRows * tileRows)))
@@ -127,12 +127,17 @@ class AccumulatorMem[T <: Data, U <: Data](
   import ev._
 
   // TODO unify this with TwoPortSyncMemIO
-  val io = IO(new AccumulatorMemIO(n, t, scale_t, acc_sub_banks, use_shared_ext_mem, use_mx_scaling, meshRows, tileRows, scale_mem.get.sramLineSizeInBytes))
+  val io = IO(new AccumulatorMemIO(n, t, scale_t, acc_sub_banks, use_shared_ext_mem, use_mx_scaling, meshRows, tileRows, scale_mem.get.bankWidthBits))
 
   val scaleFactorMem = scale_mem.map { conf =>
+    // println(s"[ScalingFactorMem Config]")
+    // println(s"  depth = ${conf.depth}")
+    // println(s"  subbankLineSizeInBytes = ${conf.subbankLineSizeInBytes}")
+    // println(s"  bankWidthBits = ${conf.bankWidthBits}")
+    // println(s"  numBanks = ${conf.numBanks}")
     Module(new ScalingFactorMem(
       depth = conf.depth,
-      bankWidth = conf.bankWidthBits,
+      sramWidth = conf.subbankLineSizeInBytes*8,
       actOutputScalingWidth = 8,
       numBanks = conf.numBanks,
       testConfig = testConfig,

src/main/scala/gemmini/ConfigsFP.scala

@@ -274,7 +274,7 @@ object GemminiMxFPConfigs {
 
                                  // 16x16 mesh with varying precisions
     scaleMem_data_width = 128,
-    scaleMem_bank_entries = 256,
+    scaleMem_bank_entries = 8192,
     scaleSize = 32,
     enable_lut = true,
     mvin_scale_args = None,
@@ -305,6 +305,7 @@ object GemminiMxFPConfigs {
 
     num_counter = 8,
     requantizer = Some(GemminiRequantizerConfig( 
+      baseAddr = 0x10000000L,
       numInputLanes = 64,
       numOutputLanes = 32,
       gpuMaxFactor = 2,
@@ -315,8 +316,10 @@ object GemminiMxFPConfigs {
       outputIdBits = 3
     )),
     scale_mem = Some(GemminiScalingFactorMemConfig(
+        baseAddr = 0x10000000L + 0x8000,
         sizeInBytes = 16 << 10,
-        sramLineSizeInBytes = 256 / 8,
+        subbankLineSizeInBytes = 16,
+        subbanksPerBank = 2,
         numBanks = 8,
         ))
   )

src/main/scala/gemmini/Controller.scala

@@ -217,32 +217,34 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data]
       val lut0 = Flipped(Decoupled(new QuantLutWriteBundle(l)))
       val lut1 = Flipped(Decoupled(new QuantLutWriteBundle(l)))
       val lut2 = Flipped(Decoupled(new QuantLutWriteBundle(l)))
+      //val scaleFactorOut = Decoupled(new ScalingFactorWriteReq(scaleMem_addr_width, scaleMem_data_width)) 
     })
 
-    if (!outer.config.testConfig) {
-      mx_io.scale_mem_write_w <> spad.module.io.scale_mem_write_w.get
-      mx_io.scale_mem_write_act <> spad.module.io.scale_mem_write_act.get
-    }
-
+    
+    spad.module.io.scale_mem_write_w.get <> mx_io.scale_mem_write_w
+    spad.module.io.scale_mem_write_act.get <> mx_io.scale_mem_write_act 
+    
+   
+    //mx_io.scaleFactorOut <> mx_requantizer.get.io.scaleMem_write
     mx_io.requant_out <> mx_requantizer.get.io.requant_data_out
     mx_requantizer.get.io.lut0_write <> mx_io.lut0
     mx_requantizer.get.io.lut1_write <> mx_io.lut1
     mx_requantizer.get.io.lut2_write <> mx_io.lut2
 
-    Seq(mx_io.requant_in_gpu, mx_io.requant_out, mx_io.lut0, mx_io.lut1, mx_io.lut2).foreach(dontTouch(_))
+    Seq(mx_io.requant_in_gpu, mx_io.requant_out, mx_io.lut0, mx_io.lut1, mx_io.lut2, mx_io.scale_mem_write_w,  mx_io.scale_mem_write_act).foreach(dontTouch(_))
     //Seq( mx_io.requant_out).foreach(dontTouch(_))
     mx_io
   }
 
 
-  spad.module.io.scale_mem_write_act.foreach { ch =>
-    ch.valid := false.B
-    ch.bits  := DontCare
-  }
-  spad.module.io.scale_mem_write_w.foreach { ch =>
-    ch.valid := false.B
-    ch.bits  := DontCare
-  }
+  // spad.module.io.scale_mem_write_act.foreach { ch =>
+  //   ch.valid := false.B
+  //   ch.bits  := DontCare
+  // }
+  // spad.module.io.scale_mem_write_w.foreach { ch =>
+  //   ch.valid := false.B
+  //   ch.bits  := DontCare
+  // }
 
   val lut_deprojected_data = Wire(Vec(sp_banks, new ScratchpadReadIO(sp_bank_entries, sp_width)))
   lut_deprojected_data := 0.U.asTypeOf(lut_deprojected_data)

src/main/scala/gemmini/ExecuteController.scala

@@ -127,14 +127,12 @@ class ExecuteController[T <: Data, U <: Data, V <: Data](xLen: Int, tagWidth: In
   val scale_mem_mvout_base_addr_act = RegInit(0.U(33.W))
 
   when(functs(0) === CONFIG_SCALE_MEM) {
-    val addr = rs1s(0).asTypeOf(new ConfigScaleMemRs1)
-    val addr_direction = addr.mem_direction
-    when(addr_direction === 0.U) { // mvin
-      val act_scale_address_rs1 = addr.mem_address
-      scale_mem_mvin_base_addr_act := act_scale_address_rs1
-      scale_mem_mvin_base_addr_w := act_scale_address_rs1 + (config.scale_mem.get.sizeInBytes >> 1).U
-    }.elsewhen(addr_direction === 1.U) { // mvout
-      scale_mem_mvout_base_addr_act := addr.mem_address
+    val direction = rs2s(0)(63) 
+    when(direction === 1.U) { // mvin
+      scale_mem_mvin_base_addr_act := rs1s(0)
+      scale_mem_mvin_base_addr_w := rs1s(0) + (config.scale_mem.get.sizeInBytes >> 1).U
+    }.elsewhen(direction === 0.U) { // mvout
+      scale_mem_mvout_base_addr_act := rs1s(0)
     }
   } 
   io.scale_mem_mvout_base_addr_act := scale_mem_mvout_base_addr_act

src/main/scala/gemmini/GemminiConfigs.scala

@@ -57,7 +57,7 @@ case class GemminiArrayConfig[T <: Data : Arithmetic, U <: Data, V <: Data](
 
 
                                                                              scaleMem_data_width: Int = 128,
-                                                                             scaleMem_bank_entries: Int = 256,
+                                                                             scaleMem_bank_entries: Int = 8192,
                                                                              scaleSize: Int = 32,
 
                                                                              dma_maxbytes: Int = 64, // TODO get this from cacheblockbytes

src/main/scala/gemmini/MxConfigFragments.scala

@@ -6,13 +6,15 @@ import chisel3.util._
 case class GemminiScalingFactorMemConfig(
   baseAddr: BigInt = 0x10000000L,
   sizeInBytes: BigInt = 16 << 10,
-  sramLineSizeInBytes: Int = 32,
+  subbankLineSizeInBytes: Int = 16,
+  subbanksPerBank: Int = 2,
   numBanks: Int = 8,
 ) {
-  def depth: Int = (sizeInBytes / sramLineSizeInBytes / numBanks).toInt
-  def bankWidthBits = sramLineSizeInBytes * 8
+  def depth: Int = (sizeInBytes / (subbankLineSizeInBytes) / numBanks).toInt
+  def bankWidthBytes = subbankLineSizeInBytes * subbanksPerBank
+  def bankWidthBits = bankWidthBytes * 8
   def addrBits = log2Ceil(sizeInBytes)
-  def lineOffsetBits = log2Ceil(sramLineSizeInBytes)
+  def lineOffsetBits = log2Ceil(bankWidthBytes) 
 }
 
 case class GemminiRequantizerConfig(
@@ -47,12 +49,13 @@ object RequantizerDataType extends ChiselEnum {
   }
 }
 
+
 class ScalingFactorWriteReq(addrWidth: Int, dataWidth: Int) extends Bundle {
   val addr = UInt(addrWidth.W)
   val data = UInt(dataWidth.W)
   def this(config: GemminiScalingFactorMemConfig) = {
     // writes two interleaved banks at once
-    this(config.addrBits, config.bankWidthBits * 2)
+    this(config.addrBits, config.bankWidthBits)
   }
 }
 

src/main/scala/gemmini/MxRequantizer.scala

@@ -289,7 +289,7 @@ class MxRequantizer[T <: Data: Arithmetic](
   // }.otherwise {
   //   quantLut.io.lut_write.ready := false.B
   // }
-
+  
   quantLut.io.lut_write_weight <> io.lut0_write
   quantLut.io.lut_write_act_in <> io.lut1_write
   quantLut.io.lut_write_act_out <> io.lut2_write
@@ -330,7 +330,6 @@ class MxRequantizer[T <: Data: Arithmetic](
 
   val scale_write_counter = RegInit(0.U(log2Ceil(scaleSize).W))
   val scale_buffer_full = RegInit(false.B)
-
   when(should_compute) {
     for (i <- 0 until scaleSize) {
       when(i.U === scale_write_counter) {
@@ -342,8 +341,12 @@ class MxRequantizer[T <: Data: Arithmetic](
       scale_buffer_full := true.B
     }.otherwise {
       scale_write_counter := scale_write_counter + 1.U
-      scale_buffer_full := false.B
+      when(io.scaleMem_write.ready){
+        scale_buffer_full := false.B
+      }
     }
+  }.elsewhen(io.scaleMem_write.ready){
+      scale_buffer_full := false.B
   }
 
   when(scale_buffer_full) {

src/main/scala/gemmini/ScaleFactorMem.scala

@@ -28,7 +28,7 @@ class ScalingFactorMemIO(addrWidth: Int, dataWidth: Int, numRows: Int, numCols:
 
 class ScalingFactorMem(
   depth: Int = 128,                     
-  bankWidth: Int = 128,                 
+  sramWidth: Int = 128,                 
   actOutputScalingWidth: Int = 8,       
   numBanks: Int = 8,
   testConfig: Boolean = false ,
@@ -37,12 +37,12 @@ class ScalingFactorMem(
 ) extends Module {
 
   val rowAddrWidth = log2Ceil(depth)  
-  val bytesPerBank = bankWidth / 8        
+  val bytesPerBank = sramWidth / 8        
   val AddrWidth = rowAddrWidth  + log2Ceil(numBanks)     
   val bankaddressWidth = log2Ceil(numBanks) 
   val totalScales = 32
   val counterWidth = log2Ceil(totalScales)  
-  val writeDataWidth = bankWidth * 2
+  val writeDataWidth = sramWidth * 2
   val io = IO(new ScalingFactorMemIO(
     AddrWidth, 
     writeDataWidth, 
@@ -77,7 +77,7 @@ class ScalingFactorMem(
   val weight_buffer_0_read_enable = RegInit(false.B)
   val weight_buffer_1_read_enable = RegInit(false.B)
   val weight_write_counter = RegInit(0.U(8.W))
-  val write_row_addr_w = io.scale_mem_write_w.bits.addr + (write_baseAddr_w >> (log2Ceil(2*meshRows*tileRows)))
+  val write_row_addr_w = io.scale_mem_write_w.bits.addr 
 
   val weight_buffer_write_full = RegInit(false.B)
   when(io.scale_mem_write_w.fire) {
@@ -110,7 +110,7 @@ class ScalingFactorMem(
   val act_buffer_0_read_enable = RegInit(false.B)
   val act_buffer_1_read_enable = RegInit(false.B)
   val act_write_counter = RegInit(0.U(8.W))
-  val write_row_addr_act = io.scale_mem_write_act.bits.addr  + (write_baseAddr_act >> (log2Ceil(2*meshRows*tileRows)))
+  val write_row_addr_act = io.scale_mem_write_act.bits.addr 
   when(io.scale_mem_write_act.fire) {
     val write_bytes_low = io.scale_mem_write_act.bits.data(bytesPerBank * 8 - 1, 0).asTypeOf(bankDataT)
     val write_bytes_high = io.scale_mem_write_act.bits.data(bytesPerBank * 2 * 8 - 1, bytesPerBank * 8).asTypeOf(bankDataT)
@@ -142,17 +142,17 @@ class ScalingFactorMem(
   when(io.read_req.fire && io.read_req.bits.scaling_enable){
     act_read_buffer_select := ~act_read_buffer_select
     weight_read_buffer_select := ~weight_read_buffer_select
-    when(act_buffer_0_read_enable && ((act_write_counter === read_row_addr))){
+    when(act_buffer_0_read_enable && ((write_row_addr_act === read_row_addr))){
         act_buffer_0_read_enable := false.B
     }
-    when(act_buffer_1_read_enable && ((act_write_counter === read_row_addr))){
+    when(act_buffer_1_read_enable && ((write_row_addr_act === read_row_addr))){
         act_buffer_1_read_enable := false.B
     }
 
-    when(weight_buffer_0_read_enable && ((weight_write_counter === read_row_addr))){
+    when(weight_buffer_0_read_enable && ((write_row_addr_w === read_row_addr))){
       weight_buffer_0_read_enable := false.B
     }
-    when(weight_buffer_1_read_enable && ((weight_write_counter === read_row_addr))){
+    when(weight_buffer_1_read_enable && ((write_row_addr_w === read_row_addr))){
       weight_buffer_1_read_enable := false.B
     }
   }
@@ -188,8 +188,8 @@ class ScalingFactorMem(
     read_fire_real && act_buffer_1_read_enable && weight_buffer_1_read_enable && (act_bank_sel === 3.U),     // bank 3
     read_fire_real && weight_buffer_0_read_enable && act_buffer_0_read_enable && (weight_bank_sel === 0.U),  // bank 4
     read_fire_real && weight_buffer_0_read_enable && act_buffer_0_read_enable && (weight_bank_sel === 1.U),  // bank 5
-    read_fire_real && weight_buffer_1_read_enable && act_buffer_0_read_enable && (weight_bank_sel === 2.U),  // bank 6
-    read_fire_real && weight_buffer_1_read_enable && act_buffer_0_read_enable && (weight_bank_sel === 3.U)  // bank 7
+    read_fire_real && weight_buffer_1_read_enable && weight_buffer_1_read_enable && (weight_bank_sel === 2.U),  // bank 6
+    read_fire_real && weight_buffer_1_read_enable && weight_buffer_1_read_enable && (weight_bank_sel === 3.U)  // bank 7
   ))