rename scaling fac out interface for consistency

Author: richardyrh

src/main/scala/gemmini/Controller.scala

@@ -217,15 +217,15 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data]
       val lut0 = Flipped(Decoupled(new QuantLutWriteBundle(l)))
       val lut1 = Flipped(Decoupled(new QuantLutWriteBundle(l)))
       val lut2 = Flipped(Decoupled(new QuantLutWriteBundle(l)))
-      //val scaleFactorOut = Decoupled(new ScalingFactorWriteReq(s.ScaleMemWriteAddrWidth, s.ScaleMemWriteAddrWidth)) 
+      val scale_factor_out = Decoupled(new ScalingFactorWriteReq(s.ScaleMemWriteAddrWidth, s.ScaleMemWriteAddrWidth))
     })
 
 
     spad.module.io.scale_mem_write_w.get <> mx_io.scale_mem_write_w
     spad.module.io.scale_mem_write_act.get <> mx_io.scale_mem_write_act 
 
 
-    //mx_io.scaleFactorOut <> mx_requantizer.get.io.scaleMem_write
+    mx_io.scale_factor_out <> mx_requantizer.get.io.scaleMem_write
     mx_io.requant_out <> mx_requantizer.get.io.requant_data_out
     mx_requantizer.get.io.lut0_write <> mx_io.lut0
     mx_requantizer.get.io.lut1_write <> mx_io.lut1

src/main/scala/gemmini/MxPE.scala

@@ -121,8 +121,8 @@ class MxPE(mxparameters: MxParams, lut: Boolean) extends Module {
   val flexMults = Seq.fill(2,2){ Module(new MACU(lut)) }
   val outFM = Wire(Vec(4, UInt(mxparameters.multOutWidth.W)))
 
-  printf(p"enable: ${io.enable}, mask_a: ${Binary(io.mask_a)}, mask_w: ${Binary(io.mask_w)}\n")  // --- IGNORE ---
-  printf(p"in_a: ${Binary(io.in_a)}, in_w: ${Binary(io.in_w)}\n")  // --- IGNORE ---
+  // printf(p"enable: ${io.enable}, mask_a: ${Binary(io.mask_a)}, mask_w: ${Binary(io.mask_w)}\n")  // --- IGNORE ---
+  // printf(p"in_a: ${Binary(io.in_a)}, in_w: ${Binary(io.in_w)}\n")  // --- IGNORE ---
 
   for (i <- 0 until 2) {
     for (j <- 0 until 2) {