change mx format definition for consistency

Author: Amanda Shi

src/main/scala/gemmini/Controller.scala

@@ -320,7 +320,7 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data]
       mx_requantizer.get.io.requant_data_in.valid := false.B
       mx_requantizer.get.io.requant_data_in.bits := DontCare
 
-      when(ex_controller.io.output_MxFormat === 2.U){
+      when(ex_controller.io.output_MxFormat === 0.U){
          mx_requantizer.get.io.fp8_mode := true.B
       }.otherwise{
         mx_requantizer.get.io.fp8_mode := false.B}
@@ -375,11 +375,11 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data]
         mx_requantizer.get.io.requant_data_in.bits.address := 
           Cat(first_valid_addr, 0.U(log2Ceil(outer.config.sp_banks).W))
 
-        when(ex_controller.io.output_MxFormat === 0.U) {
+        when(ex_controller.io.output_MxFormat === 2.U) {
           mx_requantizer.get.io.requant_data_in.bits.dataType := RequantizerDataType.FP4
         }.elsewhen(ex_controller.io.output_MxFormat === 1.U) {
           mx_requantizer.get.io.requant_data_in.bits.dataType := RequantizerDataType.FP6
-        }.elsewhen(ex_controller.io.output_MxFormat === 2.U) {
+        }.elsewhen(ex_controller.io.output_MxFormat === 0.U) {
           mx_requantizer.get.io.requant_data_in.bits.dataType := RequantizerDataType.FP8
         }
 

src/main/scala/gemmini/ExecuteController.scala

@@ -52,7 +52,7 @@ class ExecuteController[T <: Data, U <: Data, V <: Data](xLen: Int, tagWidth: In
     val counter = new CounterEventIO()
     val b_fire = Output(Bool())
     val a_fire = Output(Bool())
-    val scale_mem_mvout_base_addr_act = Output(UInt(33.W))
+    val scale_mem_mvout_base_addr_act = Output(UInt(32.W))
     val scaleMemCntl = Output(new ScalingFactorCntl(meshRows*tileRows))
   })
 

src/main/scala/gemmini/GemminiISA.scala

@@ -226,7 +226,7 @@ object GemminiISA {
     val b_transpose = UInt(CONFIG_EX_RS1_B_TRANSPOSE_WIDTH.W)
     val a_transpose = UInt(CONFIG_EX_RS1_A_TRANSPOSE_WIDTH.W)
     val set_only_strides = UInt(CONFIG_EX_RS1_SET_ONLY_STRIDES_WIDTH.W)
-    //val enable_mxquant = UInt(CONFIG_EX_RS1_ENABLE_MXQUANT_WIDTH.W)
+    val _spacer0 = UInt(1.W)
     val uselut = UInt(CONFIG_EX_RS1_LUT_ENABLE_WIDTH.W)
     val activation = UInt(CONFIG_EX_RS1_ACTIVATION_WIDTH.W)
     val dataflow = UInt(CONFIG_EX_RS1_DATAFLOW_WIDTH.W)

src/main/scala/gemmini/MxConfigFragments.scala

@@ -45,7 +45,7 @@ case class GemminiLUTConfig(
 )
 
 object RequantizerDataType extends ChiselEnum {
-  val FP4, FP6, FP8 = Value
+  val FP8, FP6, FP4 = Value
 
   def widthBits(x: Type): UInt = {
     Mux(x === FP4, 4.U(4.W), 8.U(4.W))

src/main/scala/gemmini/MxRequantizer.scala

@@ -5,9 +5,9 @@ import chisel3.util._
 
 object MxFloatFormat {
   // Format encoding
-  val FP4 = 0.U(2.W)
+  val FP8 = 0.U(2.W)
   val FP6 = 1.U(2.W)
-  val FP8 = 2.U(2.W)
+  val FP4 = 2.U(2.W)
 
   def apply(bits: UInt): (UInt, UInt, UInt, UInt) = {
     val exp_bits = MuxLookup(bits, 4.U)(Seq(
@@ -336,20 +336,17 @@ class MxRequantizer[T <: Data: Arithmetic](
       scale_buffer_full := false.B
   }
 
-  when(scale_buffer_full) {
-    io.scaleMem_write.valid := true.B
-    io.scaleMem_write.bits.addr := scale_mem_mvout_base_addr_act + (scale_write_addr_counter << 5) //byte address, scale 32B per write
-    io.scaleMem_write.bits.data := Cat(scale_buffer.reverse)
-    
-    when(io.scaleMem_write.fire) {
-      val scale_buffer_packed = Cat(scale_buffer.reverse)
-      printf(p"[MxScaleGen]: addr=${scale_write_addr_counter}, data=0x${Hexadecimal(scale_buffer_packed)}\n")
-      
+  when(io.scaleMem_write.fire) {
       when(scale_write_addr_counter === ((1 << 10) - 1).U) {
         scale_write_addr_counter := 0.U
       }.otherwise {
         scale_write_addr_counter := scale_write_addr_counter + 1.U
       }
-    }
+  }
+
+  when(scale_buffer_full) {
+    io.scaleMem_write.valid := true.B
+    io.scaleMem_write.bits.addr := scale_mem_mvout_base_addr_act + (scale_write_addr_counter << 5) //byte address, scale 32B per write
+    io.scaleMem_write.bits.data := Cat(scale_buffer.reverse)
   }
 }

src/main/scala/gemmini/ReservationStation.scala

@@ -311,7 +311,7 @@ class ReservationStation[T <: Data : Arithmetic, U <: Data, V <: Data](config: G
     }
 
     val is_load = funct === LOAD_CMD || funct === LOAD2_CMD || funct === LOAD3_CMD || (funct === CONFIG_CMD && config_cmd_type === CONFIG_LOAD)
-    val is_ex = funct === PRELOAD_CMD || funct_is_compute || (funct === CONFIG_CMD && config_cmd_type === CONFIG_EX)
+    val is_ex = funct === PRELOAD_CMD || funct_is_compute || (funct === CONFIG_CMD && config_cmd_type === CONFIG_EX) || (funct === CONFIG_SCALE_MEM)
     val is_store = funct === STORE_CMD || funct === STORE_SPAD_CMD || (funct === CONFIG_CMD && (config_cmd_type === CONFIG_STORE || config_cmd_type === CONFIG_NORM))
     val is_norm = funct === CONFIG_CMD && config_cmd_type === CONFIG_NORM // normalization commands are a subset of store commands, so they still go in the store queue
 

src/main/scala/gemmini/Scratchpad.scala

@@ -124,21 +124,6 @@ class ScratchpadBank(n: Int, w: Int, aligned_to: Int, single_ported: Boolean, us
   val input_mx_format = io.read.req.bits.input_mx_format
 
 
-  val bits_per_element = MuxLookup(input_mx_format, 8.U)(Seq(
-    0.U -> 8.U,  // FP8
-    1.U -> 4.U,  // FP6
-    2.U -> 4.U   // FP4
-  ))
-  
-  val elements_per_row = (w / 8).U  
-  val total_bits_needed = elements_per_row * bits_per_element
-  val bytes_needed = (total_bits_needed + 7.U) >> 3.U
-  val addresses_needed = (bytes_needed + (w/8 - 1).U) / (w/8).U
-
-  
-
-
-
   // Make a queue which buffers the result of an SRAM read if it can't immediately be consumed
   val q = Module(new Queue(new ScratchpadReadResp(w), 1, true, true))
   val q_will_be_empty = (q.io.count +& q.io.enq.fire) - q.io.deq.fire === 0.U