revert tlb fix

Author: richardyrh

src/main/scala/gemmini/DMA.scala

@@ -233,7 +233,7 @@ class StreamReaderCore[T <: Data, U <: Data, V <: Data](config: GemminiArrayConf
     io.tlb.req.valid := tlb_q.io.deq.valid
     io.tlb.req.bits := DontCare
     io.tlb.req.bits.tlb_req.vaddr := tlb_q.io.deq.bits.vaddr
-    io.tlb.req.bits.tlb_req.passthrough := true.B
+    io.tlb.req.bits.tlb_req.passthrough := false.B
     io.tlb.req.bits.tlb_req.size := 0.U // send_size
     io.tlb.req.bits.tlb_req.cmd := M_XRD
     io.tlb.req.bits.status := tlb_q.io.deq.bits.status
@@ -545,7 +545,6 @@ class StreamWriter[T <: Data: Arithmetic](nXacts: Int, beatBits: Int, maxBytes:
     io.tlb.req.bits := DontCare
     io.tlb.req.bits.tlb_req.vaddr := tlb_q.io.deq.bits.vaddr
     io.tlb.req.bits.tlb_req.passthrough := tlb_q.io.deq.bits.passthrough
-    dontTouch(io.tlb.req.bits.tlb_req.passthrough)
     io.tlb.req.bits.tlb_req.size := 0.U // send_size
     io.tlb.req.bits.tlb_req.cmd := M_XWR
     io.tlb.req.bits.status := tlb_q.io.deq.bits.status

src/main/scala/gemmini/FrontendTLB.scala

@@ -148,23 +148,6 @@ class FrontendTLB(nClients: Int, entries: Int, maxSize: Int, use_tlb_register_fi
       client.resp.miss := !RegNext(l0_tlb_hit)
     }
 
-    // short-circuit passthroughs
-    val curr_req = tlbArbOpt.get.io.in(i)
-    when (tlbReqFire) {
-      dontTouch(curr_req.bits.tlb_req.passthrough)
-      when (curr_req.bits.tlb_req.passthrough) {
-        tlb.io.req.valid := false.B
-        client.resp.miss := false.B
-      }
-    }
-    when (RegNext(tlbReqFire)) {
-      when (RegNext(curr_req.bits.tlb_req.passthrough)) {
-        client.resp := 0.U.asTypeOf(client.resp)
-        client.resp.miss := false.B
-        client.resp.paddr := RegNext(curr_req.bits.tlb_req.vaddr)
-      }
-    }
-
     // If we're not using the TLB filter register, then we set this value to always be false
     if (!use_tlb_register_filter) {
       last_translated_valid := false.B