WiP: a monolithic top level co-sim bench

verilog/constants.vams

@@ -43,12 +43,18 @@
 `define DRIVER_R_OFF_SEGMENT 1000000
 
 // CLOCK_PATH
+// Clock period
+`define CLK_PERIOD 125e-12
 // Digitally-controlled delay line bit width
 `define DCDL_CTRL_BITWIDTH 8
 // Digitally-controlled delay line delay offset (ps)
 `define DCDL_DELAY_OFS 10.0
 // Digitally-controlled delay line delay sep (ps)
 `define DCDL_DELAY_STEP 10.0
+// Clock distribution mean delay
+`define CLK_DIST_DELAY_MU 200e-12
+// Clock distribution std deviation
+`define CLK_DIST_DELAY_SIGMA 0.5e-12
 
 // TX
 // TX nominal output impedance (Ohms)

verilog/dcdl.vams

@@ -81,8 +81,6 @@
 // ============================================================================
 
 `include "constants.vams"
-`include "disciplines.vams"
-`include "./constants.vams"
 
 module dcdl(clk_in, dl_ctrl, clk_out);
     input clk_in; electrical clk_in;

verilog/phy.sv

@@ -18,6 +18,7 @@ module phy(
 
 // TODO: add back after PLL model simulates faster and/or 
 // jitter simulation is needed
+// FIXME(Di): If you use the PLL model, make sure to turn on simulation noise and set the simulation time > 15us (which is the PLL lock time).  
 // bbpll pll(
 //     .reset(intf.pll_reset),
 //     .clk_out(intf.pll_clk_out),
@@ -26,9 +27,48 @@ module phy(
 
 txdriver_tile sb_txdata_drv(.intf(intf.sb_txdata));
 txdriver_tile sb_txclk_drv(.intf(intf.sb_txclk));
+wire [`LANES-1:0] txclk_sed;
+
+clocking_distribution_model #(
+    .propagation_delay_mu(`CLK_DIST_DELAY_MU),
+    .propagation_delay_sigma(`CLK_DIST_DELAY_SIGMA)
+)   clk_dist_inst(
+    .clk_in(intf.pll_clk_out),
+    .clk_out(txclk_sed)
+);
+
+wire deskewed_clk, deskewed_clkp, deskewed_clkn;
+dcdl #(
+    .delay_gain(0),
+    .delay_offset(`CLK_DIST_DELAY_MU + `CLK_PERIOD/4)
+) dcdl_inst(
+    .clk_in(intf.pll_clk_out),
+    .dl_ctrl(0),
+    .clk_out(deskewed_clk)
+);
+
+s2d s2d_clklane_inst(
+    .clk_in(deskewed_clk),
+    .clk_outp(deskewed_clkp),
+    .clk_outn(deskewed_clkn)
+);
+assign intf.txclkp.clkp = deskewed_clkp;
+assign intf.txclkp.clkn = deskewed_clkn;
+assign intf.txclkn.clkp = deskewed_clkp;
+assign intf.txclkn.clkn = deskewed_clkn;
+assign intf.txval.clkp = deskewed_clkp;
+assign intf.txval.clkn = deskewed_clkn;
+assign intf.txtrk.clkp = deskewed_clkp;
+assign intf.txtrk.clkn = deskewed_clkn;
+
 genvar i;
 generate
     for(i = 0; i < `LANES; i++) begin
+        s2d s2d_inst(
+            .clk_in(txclk_sed[i]),
+            .clk_outp(intf.txdata[i].clkp),
+            .clk_outn(intf.txdata[i].clkn)
+        );
         txdata_tile txdata_tile(.intf(intf.txdata[i]));
     end
 endgenerate
@@ -52,13 +92,14 @@ endmodule
 module phy_tb;
     wire vdd = 1, vss = 0;
     reg reset = 1;
-    reg clkp;
-    wire clkn;
+    reg pll_clkp_out;
+    wire pll_clkn_out;
+
     reg a_en, a_pc, b_en, b_pc, sel_a, din_dig;
 
-    initial clkp = 0;
-    always #(`MIN_PERIOD/2) clkp = ~clkp;
-    assign clkn = ~clkp;
+    initial pll_clkp_out = 0;
+    always #(`MIN_PERIOD/2) pll_clkp_out = ~pll_clkp_out;
+    assign pll_clkn_out = ~pll_clkp_out;
 
     initial begin
         a_pc = 1;
@@ -101,8 +142,8 @@ module phy_tb;
     );
 
     assign intf.pll_reset = reset;
-    assign intf.pll_Dctrl_value = 1;
-
+    assign intf.pll_Dctrl_value = 1; // FIXME(Di): pll_Dctrl_value is an output showing the internal locking status of the PLL, so don't tie it to 1.
+    assign intf.pll_clk_out = pll_clkp_out;
     assign intf.sb_txdata.vdd = vdd;
     assign intf.sb_txdata.vss = vss;
     assign intf.sb_txdata.pu_ctl = 0;
@@ -123,8 +164,6 @@ module phy_tb;
             assign intf.txdata[i].vdd = vdd;
             assign intf.txdata[i].vss = vss;
             assign intf.txdata[i].din = {2**(`SERDES_STAGES-1){2'b01}};
-            assign intf.txdata[i].clkp = clkp;
-            assign intf.txdata[i].clkn = clkn;
             assign intf.txdata[i].rstb = ~reset;
             assign intf.txdata[i].pu_ctl = 0;
             assign intf.txdata[i].pd_ctlb = {`DRIVER_CTL_BITS{1'b1}};
@@ -151,8 +190,6 @@ module phy_tb;
     assign intf.txclkp.vdd = vdd;
     assign intf.txclkp.vss = vss;
     assign intf.txclkp.din = {2**(`SERDES_STAGES-1){2'b01}};
-    assign intf.txclkp.clkp = clkp;
-    assign intf.txclkp.clkn = clkn;
     assign intf.txclkp.rstb = ~reset;
     assign intf.txclkp.pu_ctl = 0;
     assign intf.txclkp.pd_ctlb = {`DRIVER_CTL_BITS{1'b1}};
@@ -163,8 +200,6 @@ module phy_tb;
     assign intf.txclkn.vdd = vdd;
     assign intf.txclkn.vss = vss;
     assign intf.txclkn.din = {2**(`SERDES_STAGES-1){2'b10}};
-    assign intf.txclkn.clkp = clkp;
-    assign intf.txclkn.clkn = clkn;
     assign intf.txclkn.rstb = ~reset;
     assign intf.txclkn.pu_ctl = 0;
     assign intf.txclkn.pd_ctlb = {`DRIVER_CTL_BITS{1'b1}};
@@ -175,8 +210,6 @@ module phy_tb;
     assign intf.txval.vdd = vdd;
     assign intf.txval.vss = vss;
     assign intf.txval.din = {2**(`SERDES_STAGES-3){8'hf0}};
-    assign intf.txval.clkp = clkp;
-    assign intf.txval.clkn = clkn;
     assign intf.txval.rstb = ~reset;
     assign intf.txval.pu_ctl = 0;
     assign intf.txval.pd_ctlb = {`DRIVER_CTL_BITS{1'b1}};
@@ -187,8 +220,6 @@ module phy_tb;
     assign intf.txtrk.vdd = vdd;
     assign intf.txtrk.vss = vss;
     assign intf.txtrk.din = {2**(`SERDES_STAGES-1){2'b01}};
-    assign intf.txtrk.clkp = clkp;
-    assign intf.txtrk.clkn = clkn;
     assign intf.txtrk.rstb = ~reset;
     assign intf.txtrk.pu_ctl = 0;
     assign intf.txtrk.pd_ctlb = {`DRIVER_CTL_BITS{1'b1}};

xcelium/Makefile

@@ -0,0 +1,57 @@
+XRUN := xrun
+XRUN_OPTS := -sv_ms \
+             -dmsaoi \
+             -timescale 1ps/1fs \
+             -access +rwc \
+             -iereport \
+			 -plusperf \
+			 -64bit \
+			 -spectre_args "+preset=cx +mt=32" \
+			 -CFLAGS "-std=c++11 -g"
+VAMS_DIR := ../verilog
+# SPECTRE_HOME := /tools/cadence/SPECTRE/SPECTRE251
+# XCELIUM_HOME := /tools/cadence/XCELIUM/XCELIUM2409.006/
+INCLUDES := -incdir $(VAMS_DIR) -incdir $(SPECTRE_HOME)/tools.lnx86/spectre/etc/ahdl
+PHY_PROBE := probe.tcl
+
+# Source files
+DISCIPLINES := $(SPECTRE_HOME)/tools.lnx86/spectre/etc/ahdl/disciplines.vams
+CONSTANTS := $(VAMS_DIR)/constants.vams
+PRIMITIVES_SV := $(VAMS_DIR)/primitives.sv
+PRIMITIVES_VAMS := $(VAMS_DIR)/primitives.vams
+TX_SRC := $(VAMS_DIR)/tx.sv
+TX_VAMS := $(VAMS_DIR)/tx.vams
+RX_SRC := $(VAMS_DIR)/rx.sv
+RX_VAMS := $(VAMS_DIR)/rx.vams
+PHY_SRC := $(VAMS_DIR)/phy.sv
+# bbpll.vams, dcdl.vams, s2d.vams, clock_distribution.vams
+CLOCKING_SRC := $(VAMS_DIR)/dcdl.vams $(VAMS_DIR)/s2d.vams $(VAMS_DIR)/clock_distribution.vams
+
+
+phy:
+	@echo "=========================================="
+	@echo "Running UCIePHY Testbench with xrun..."
+	@echo "=========================================="
+	$(XRUN) $(XRUN_OPTS) \
+		$(DISCIPLINES) \
+		$(CONSTANTS) \
+		$(PRIMITIVES_VAMS) \
+		$(TX_VAMS) \
+		$(RX_VAMS) \
+		$(PRIMITIVES_SV) \
+		$(TX_SRC) \
+		$(RX_SRC) \
+		$(PHY_SRC) \
+		$(CLOCKING_SRC) \
+		amscf.scs \
+		-reflib $(XCELIUM_HOME)/tools.lnx86/affirma_ams/etc/connect_lib/connectLib:uCR \
+		-amsconnrules uCR \
+		-top phy_tb \
+		-input $(PHY_PROBE)
+	@echo "UCIePHY simulation completed. Waveforms: phy_waves.shm"
+	@echo ""
+
+clean:
+	@echo "Cleaning simulation outputs..."
+	@rm -rf worklib *.log *.shm *.diag INCA_libs xcelium.d .simvision xrun.history .cadence worklibxrun amscf.ams
+	@echo "Clean complete."

xcelium/README.md

@@ -0,0 +1,45 @@
+# Xcelium UCIePHY Simulation Project
+
+This directory contains the Xcelium simulation setup for the UCIePHY (Universal Chiplet Interconnect Express Physical Layer) testbench. The simulation uses mixed-signal (AMS + SystemVerilog) modeling to verify the PHY components.
+
+## Prerequisites
+
+Before running the simulation, you **must** define the following environment variables to point to your Cadence tool installations:
+
+- **SPECTRE_HOME**: Path to the Spectre installation directory.
+- **AMS_HOME**: Path to the Xcelium AMS installation directory.
+
+Without these variables, the Makefile will fail to locate necessary libraries and disciplines.
+
+## Running the Simulation
+
+1. Ensure you are in the `xcelium` directory.
+2. Set the environment variables as described above.
+3. Run the simulation:
+
+   ```bash
+   make phy
+   ```
+
+   This will compile all AMS and SystemVerilog sources, elaborate the design, and run the testbench with the top-level module `phy_tb`.
+
+## Cleaning Up
+
+To remove simulation artifacts (libraries, logs, waveforms):
+
+```bash
+make clean
+```
+
+## Files Overview
+
+- **Makefile**: Defines the simulation flow using `xrun`.
+- **amscf.scs**: AMS control file for Spectre integration.
+- **probe.tcl**: Tcl script for waveform probing.
+- **../verilog/**: Source files (AMS and SV) for the PHY components.
+
+## Notes
+
+- The simulation uses mixed-signal mode (`-sv_ms`) to handle both analog (AMS) and digital (SystemVerilog) components.
+- Waveforms are saved to `phy_waves.shm` upon completion.
+- If you encounter permission or path errors, verify the environment variables and tool installations.

xcelium/amscf.scs

@@ -3,10 +3,13 @@
 // ****************************************************************
 simulator lang=spectre 
 
-global 0
+global 0 vdd!
 
 amsd {
-    ie vsup=0.75 tr=5p tf=5p rout=0
+    ie vsup=0.75 tr=20p tf=20p rout=0
 }
 
-tran tran stop=1u annotate=status
+
+tran tran stop=1u noisefmax=64G noiseseed=32 annotate=status
+// to disable noise, comment the above line and uncomment the line below
+//tran tran stop=1u annotate=status