Added koios_sv/deepfreeze.style1.sv to vtr_reg_system_verilog and created golden results

loglav03 · loglav03 · commit 0cda1bf9cb62 · 2025-07-11T15:27:16.000-03:00
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/koios_sv/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/koios_sv/config/golden_results.txt
@@ -0,0 +1,2 @@
+arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
+k6_frac_N10_frac_chain_mem32K_40nm.xml	deepfreeze.style1.sv	common	436.14	parmys	1.86 GiB		-1	-1	411.69	1951548	3	0.26	-1	-1	39048	-1	-1	569	3	0	0	success	v8.0.0-13294-ga4090df7f-dirty	release IPO VTR_ASSERT_LEVEL=2 debug_logging	GNU 11.4.0 on Linux-6.8.0-60-generic x86_64	2025-07-11T13:46:55	llavign1-OptiPlex-7070	/home/llavign1/Gits/vtr-clone/vtr_flow/scripts	84760	3	513	1838	2166	1	824	1085	30	30	900	clb	auto	41.9 MiB	0.69	4207.31	1231	575104	399781	38987	136336	82.6 MiB	0.70	0.01	4.09934	2.34735	-601.556	-2.34735	2.34735	0.70	0.00153716	0.00141826	0.186598	0.172244	-1	-1	-1	-1	26	2161	10	4.8774e+07	3.06657e+07	1.76811e+06	1964.57	2.04	0.502771	0.465859	83012	347295	-1	1972	8	569	767	17591	4270	2.4085	2.4085	-599.698	-2.4085	0	0	2.17697e+06	2418.86	0.08	0.06	0.18	-1	-1	0.08	0.0661326	0.0635241	
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/task_list.txt
@@ -1,4 +1,4 @@
 regression_tests/vtr_reg_system_verilog/f4pga_button_controller/
-#regression_tests/vtr_reg_system_verilog/koios_sv/
+regression_tests/vtr_reg_system_verilog/koios_sv/
 regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/
 regression_tests/vtr_reg_system_verilog/f4pga_timer/

Original file line number	Diff line number	Diff line change
`@@ -0,0 +1,2 @@`
	`1`	+arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
	`2`	+k6_frac_N10_frac_chain_mem32K_40nm.xml deepfreeze.style1.sv common 436.14 parmys 1.86 GiB -1 -1 411.69 1951548 3 0.26 -1 -1 39048 -1 -1 569 3 0 0 success v8.0.0-13294-ga4090df7f-dirty release IPO VTR_ASSERT_LEVEL=2 debug_logging GNU 11.4.0 on Linux-6.8.0-60-generic x86_64 2025-07-11T13:46:55 llavign1-OptiPlex-7070 /home/llavign1/Gits/vtr-clone/vtr_flow/scripts 84760 3 513 1838 2166 1 824 1085 30 30 900 clb auto 41.9 MiB 0.69 4207.31 1231 575104 399781 38987 136336 82.6 MiB 0.70 0.01 4.09934 2.34735 -601.556 -2.34735 2.34735 0.70 0.00153716 0.00141826 0.186598 0.172244 -1 -1 -1 -1 26 2161 10 4.8774e+07 3.06657e+07 1.76811e+06 1964.57 2.04 0.502771 0.465859 83012 347295 -1 1972 8 569 767 17591 4270 2.4085 2.4085 -599.698 -2.4085 0 0 2.17697e+06 2418.86 0.08 0.06 0.18 -1 -1 0.08 0.0661326 0.0635241