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Merge pull request #3206 from verilog-to-routing/rr_drawing_update
Cleaned up RRGraph Drawing Code
2 parents 0624c71 + a75261f commit 770be34

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7 files changed

+275
-450
lines changed

7 files changed

+275
-450
lines changed

vpr/src/base/read_blif.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -538,9 +538,9 @@ struct BlifAllocCallback : public blifparse::Callback {
538538
bool verify_blackbox_model(AtomNetlist& blif_model) {
539539
LogicalModelId arch_model_id = models_.get_model_by_name(blif_model.netlist_name());
540540

541-
if(!arch_model_id.is_valid()) {
541+
if (!arch_model_id.is_valid()) {
542542
vpr_throw(VPR_ERROR_BLIF_F, filename_.c_str(), lineno_, "BLIF model '%s' has no equivalent architecture model.",
543-
blif_model.netlist_name().c_str());
543+
blif_model.netlist_name().c_str());
544544
}
545545

546546
const t_model& arch_model = models_.get_model(arch_model_id);

vpr/src/draw/draw_basic.cpp

Lines changed: 2 additions & 153 deletions
Original file line numberDiff line numberDiff line change
@@ -609,172 +609,21 @@ void draw_routed_net(ParentNetId net_id, ezgl::renderer* g) {
609609
//Draws the set of rr_nodes specified, using the colors set in draw_state
610610
void draw_partial_route(const std::vector<RRNodeId>& rr_nodes_to_draw, ezgl::renderer* g) {
611611
t_draw_state* draw_state = get_draw_state_vars();
612-
auto& device_ctx = g_vpr_ctx.device();
613-
const auto& rr_graph = device_ctx.rr_graph;
614612

615613
// Draw RR Nodes
616614
for (size_t i = 1; i < rr_nodes_to_draw.size(); ++i) {
617615
RRNodeId inode = rr_nodes_to_draw[i];
618-
e_rr_type rr_type = rr_graph.node_type(inode);
619-
bool is_inode_inter_cluster = is_inter_cluster_node(rr_graph, inode);
620-
int node_layer = rr_graph.node_layer(inode);
621-
622616
ezgl::color color = draw_state->draw_rr_node[inode].color;
623617

624-
// For 3D architectures, draw only visible layers
625-
if (!draw_state->draw_layer_display[node_layer].visible) {
626-
continue;
627-
}
628-
629-
// Skip drawing sources and sinks
630-
if (rr_type == e_rr_type::SINK || rr_type == e_rr_type::SOURCE) {
631-
continue;
632-
}
633-
634-
// Draw intra-cluster nodes
635-
if (!is_inode_inter_cluster) {
636-
draw_rr_intra_cluster_pin(inode, color, g);
637-
continue;
638-
}
639-
640-
// Draw cluster-level IO Pins
641-
if (rr_type == e_rr_type::OPIN || rr_type == e_rr_type::IPIN) {
642-
draw_cluster_pin(inode, color, g);
643-
continue;
644-
}
645-
646-
// Draw Channels
647-
if (rr_type == e_rr_type::CHANY || rr_type == e_rr_type::CHANX) {
648-
draw_rr_chan(inode, color, g);
649-
continue;
650-
}
618+
draw_rr_node(inode, color, g);
651619
}
652620

653621
// Draw Edges
654622
for (size_t i = 1; i < rr_nodes_to_draw.size(); ++i) {
655-
656623
RRNodeId inode = rr_nodes_to_draw[i];
657-
auto rr_type = rr_graph.node_type(inode);
658-
bool inode_inter_cluster = is_inter_cluster_node(rr_graph, inode);
659-
int current_node_layer = rr_graph.node_layer(inode);
660-
661624
RRNodeId prev_node = rr_nodes_to_draw[i - 1];
662-
auto prev_type = rr_graph.node_type(RRNodeId(prev_node));
663-
bool prev_node_inter_cluster = is_inter_cluster_node(rr_graph, prev_node);
664-
int prev_node_layer = rr_graph.node_layer(prev_node);
665-
666-
t_draw_layer_display edge_visibility = get_element_visibility_and_transparency(prev_node_layer, current_node_layer);
667-
ezgl::color color = draw_state->draw_rr_node[inode].color;
668-
669-
// For 3D architectures, draw only visible layers
670-
if (!draw_state->draw_layer_display[current_node_layer].visible || !edge_visibility.visible) {
671-
continue;
672-
}
673-
674-
// Skip drawing edges to or from sources and sinks
675-
if (rr_type == e_rr_type::SINK || rr_type == e_rr_type::SOURCE || prev_type == e_rr_type::SINK || prev_type == e_rr_type::SOURCE) {
676-
continue;
677-
}
678-
679-
g->set_color(color, edge_visibility.alpha);
680-
681-
if (!inode_inter_cluster && !prev_node_inter_cluster) {
682-
draw_intra_cluster_edge(inode, prev_node, g);
683-
continue;
684-
}
685625

686-
// Default side for pin in case none can be found
687-
e_side pin_side = e_side::TOP;
688-
if (!prev_node_inter_cluster && inode_inter_cluster) {
689-
// draw intra-cluster pin to inter-cluster pin
690-
// node i + 1 is the channel node
691-
if (i + 1 < rr_nodes_to_draw.size()) {
692-
pin_side = get_pin_side(inode, rr_nodes_to_draw[i + 1]);
693-
}
694-
695-
draw_intra_cluster_pin_to_pin(prev_node, inode, FROM_INTRA_CLUSTER_TO_INTER_CLUSTER, pin_side, g);
696-
continue;
697-
}
698-
699-
if (prev_node_inter_cluster && !inode_inter_cluster) {
700-
// draw inter-cluster pin to intra-cluster pin
701-
// node i - 2 is the channel node
702-
if (i >= 2) {
703-
pin_side = get_pin_side(prev_node, rr_nodes_to_draw[i - 2]);
704-
}
705-
706-
draw_intra_cluster_pin_to_pin(inode, prev_node, FROM_INTER_CLUSTER_TO_INTRA_CLUSTER, pin_side, g);
707-
continue;
708-
}
709-
710-
draw_inter_cluster_rr_edge(inode, prev_node, rr_type, prev_type, g);
711-
}
712-
}
713-
714-
void draw_inter_cluster_rr_edge(RRNodeId inode, RRNodeId prev_node, e_rr_type rr_type, e_rr_type prev_type, ezgl::renderer* g) {
715-
const RRGraphView& rr_graph = g_vpr_ctx.device().rr_graph;
716-
t_edge_size iedge = find_edge(prev_node, inode);
717-
short switch_type = rr_graph.edge_switch(RRNodeId(prev_node), iedge);
718-
719-
switch (rr_type) {
720-
case e_rr_type::IPIN: {
721-
if (prev_type == e_rr_type::OPIN) {
722-
draw_pin_to_pin(prev_node, inode, g);
723-
} else {
724-
draw_pin_to_chan_edge(inode, prev_node, g);
725-
}
726-
break;
727-
}
728-
case e_rr_type::CHANX: {
729-
switch (prev_type) {
730-
case e_rr_type::CHANX: {
731-
draw_chanx_to_chanx_edge(prev_node, inode, switch_type, g);
732-
break;
733-
}
734-
case e_rr_type::CHANY: {
735-
draw_chanx_to_chany_edge(inode, prev_node, FROM_Y_TO_X, switch_type, g);
736-
break;
737-
}
738-
case e_rr_type::OPIN: {
739-
draw_pin_to_chan_edge(prev_node, inode, g);
740-
break;
741-
}
742-
default: {
743-
VPR_ERROR(VPR_ERROR_OTHER,
744-
"Unexpected connection from an rr_node of type %d to one of type %d.\n",
745-
prev_type, rr_type);
746-
}
747-
}
748-
break;
749-
}
750-
case e_rr_type::CHANY: {
751-
switch (prev_type) {
752-
case e_rr_type::CHANX: {
753-
draw_chanx_to_chany_edge(prev_node, inode,
754-
FROM_X_TO_Y, switch_type, g);
755-
break;
756-
}
757-
case e_rr_type::CHANY: {
758-
draw_chany_to_chany_edge(RRNodeId(prev_node), RRNodeId(inode),
759-
switch_type, g);
760-
break;
761-
}
762-
case e_rr_type::OPIN: {
763-
draw_pin_to_chan_edge(prev_node, inode, g);
764-
765-
break;
766-
}
767-
default: {
768-
VPR_ERROR(VPR_ERROR_OTHER,
769-
"Unexpected connection from an rr_node of type %d to one of type %d.\n",
770-
prev_type, rr_type);
771-
}
772-
}
773-
break;
774-
}
775-
default: {
776-
break;
777-
}
626+
draw_rr_edge(inode, prev_node, draw_state->draw_rr_node[inode].color, g);
778627
}
779628
}
780629

vpr/src/draw/draw_basic.h

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -57,13 +57,6 @@ void draw_routed_net(ParentNetId net, ezgl::renderer* g);
5757
void draw_partial_route(const std::vector<RRNodeId>& rr_nodes_to_draw,
5858
ezgl::renderer* g);
5959

60-
/** @brief Draws an edge between two rr_nodes, which are both intra-cluster nodes.
61-
* @param inode The current rr_node id
62-
* @param prev_node The previous rr_node id
63-
* @param g The ezgl renderer
64-
*/
65-
void draw_inter_cluster_rr_edge(RRNodeId inode, RRNodeId prev_node, e_rr_type rr_type, e_rr_type prev_type, ezgl::renderer* g);
66-
6760
/**
6861
* @brief Returns the layer number of a timing path node
6962
* @param node

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