@@ -609,172 +609,21 @@ void draw_routed_net(ParentNetId net_id, ezgl::renderer* g) {
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// Draws the set of rr_nodes specified, using the colors set in draw_state
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void draw_partial_route (const std::vector<RRNodeId>& rr_nodes_to_draw, ezgl::renderer* g) {
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t_draw_state* draw_state = get_draw_state_vars ();
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- auto & device_ctx = g_vpr_ctx.device ();
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- const auto & rr_graph = device_ctx.rr_graph ;
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// Draw RR Nodes
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for (size_t i = 1 ; i < rr_nodes_to_draw.size (); ++i) {
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RRNodeId inode = rr_nodes_to_draw[i];
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- e_rr_type rr_type = rr_graph.node_type (inode);
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- bool is_inode_inter_cluster = is_inter_cluster_node (rr_graph, inode);
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- int node_layer = rr_graph.node_layer (inode);
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-
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ezgl::color color = draw_state->draw_rr_node [inode].color ;
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- // For 3D architectures, draw only visible layers
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- if (!draw_state->draw_layer_display [node_layer].visible ) {
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- continue ;
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- }
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-
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- // Skip drawing sources and sinks
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- if (rr_type == e_rr_type::SINK || rr_type == e_rr_type::SOURCE) {
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- continue ;
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- }
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-
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- // Draw intra-cluster nodes
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- if (!is_inode_inter_cluster) {
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- draw_rr_intra_cluster_pin (inode, color, g);
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- continue ;
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- }
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-
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- // Draw cluster-level IO Pins
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- if (rr_type == e_rr_type::OPIN || rr_type == e_rr_type::IPIN) {
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- draw_cluster_pin (inode, color, g);
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- continue ;
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- }
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-
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- // Draw Channels
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- if (rr_type == e_rr_type::CHANY || rr_type == e_rr_type::CHANX) {
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- draw_rr_chan (inode, color, g);
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- continue ;
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- }
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+ draw_rr_node (inode, color, g);
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}
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// Draw Edges
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for (size_t i = 1 ; i < rr_nodes_to_draw.size (); ++i) {
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-
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RRNodeId inode = rr_nodes_to_draw[i];
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- auto rr_type = rr_graph.node_type (inode);
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- bool inode_inter_cluster = is_inter_cluster_node (rr_graph, inode);
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- int current_node_layer = rr_graph.node_layer (inode);
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-
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RRNodeId prev_node = rr_nodes_to_draw[i - 1 ];
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- auto prev_type = rr_graph.node_type (RRNodeId (prev_node));
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- bool prev_node_inter_cluster = is_inter_cluster_node (rr_graph, prev_node);
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- int prev_node_layer = rr_graph.node_layer (prev_node);
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-
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- t_draw_layer_display edge_visibility = get_element_visibility_and_transparency (prev_node_layer, current_node_layer);
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- ezgl::color color = draw_state->draw_rr_node [inode].color ;
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-
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- // For 3D architectures, draw only visible layers
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- if (!draw_state->draw_layer_display [current_node_layer].visible || !edge_visibility.visible ) {
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- continue ;
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- }
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-
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- // Skip drawing edges to or from sources and sinks
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- if (rr_type == e_rr_type::SINK || rr_type == e_rr_type::SOURCE || prev_type == e_rr_type::SINK || prev_type == e_rr_type::SOURCE) {
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- continue ;
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- }
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-
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- g->set_color (color, edge_visibility.alpha );
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-
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- if (!inode_inter_cluster && !prev_node_inter_cluster) {
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- draw_intra_cluster_edge (inode, prev_node, g);
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- continue ;
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- }
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- // Default side for pin in case none can be found
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- e_side pin_side = e_side::TOP;
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- if (!prev_node_inter_cluster && inode_inter_cluster) {
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- // draw intra-cluster pin to inter-cluster pin
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- // node i + 1 is the channel node
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- if (i + 1 < rr_nodes_to_draw.size ()) {
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- pin_side = get_pin_side (inode, rr_nodes_to_draw[i + 1 ]);
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- }
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-
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- draw_intra_cluster_pin_to_pin (prev_node, inode, FROM_INTRA_CLUSTER_TO_INTER_CLUSTER, pin_side, g);
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- continue ;
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- }
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-
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- if (prev_node_inter_cluster && !inode_inter_cluster) {
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- // draw inter-cluster pin to intra-cluster pin
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- // node i - 2 is the channel node
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- if (i >= 2 ) {
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- pin_side = get_pin_side (prev_node, rr_nodes_to_draw[i - 2 ]);
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- }
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-
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- draw_intra_cluster_pin_to_pin (inode, prev_node, FROM_INTER_CLUSTER_TO_INTRA_CLUSTER, pin_side, g);
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- continue ;
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- }
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-
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- draw_inter_cluster_rr_edge (inode, prev_node, rr_type, prev_type, g);
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- }
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- }
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-
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- void draw_inter_cluster_rr_edge (RRNodeId inode, RRNodeId prev_node, e_rr_type rr_type, e_rr_type prev_type, ezgl::renderer* g) {
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- const RRGraphView& rr_graph = g_vpr_ctx.device ().rr_graph ;
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- t_edge_size iedge = find_edge (prev_node, inode);
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- short switch_type = rr_graph.edge_switch (RRNodeId (prev_node), iedge);
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-
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- switch (rr_type) {
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- case e_rr_type::IPIN: {
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- if (prev_type == e_rr_type::OPIN) {
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- draw_pin_to_pin (prev_node, inode, g);
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- } else {
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- draw_pin_to_chan_edge (inode, prev_node, g);
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- }
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- break ;
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- }
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- case e_rr_type::CHANX: {
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- switch (prev_type) {
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- case e_rr_type::CHANX: {
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- draw_chanx_to_chanx_edge (prev_node, inode, switch_type, g);
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- break ;
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- }
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- case e_rr_type::CHANY: {
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- draw_chanx_to_chany_edge (inode, prev_node, FROM_Y_TO_X, switch_type, g);
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- break ;
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- }
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- case e_rr_type::OPIN: {
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- draw_pin_to_chan_edge (prev_node, inode, g);
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- break ;
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- }
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- default : {
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- VPR_ERROR (VPR_ERROR_OTHER,
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- " Unexpected connection from an rr_node of type %d to one of type %d.\n " ,
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- prev_type, rr_type);
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- }
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- }
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- break ;
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- }
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- case e_rr_type::CHANY: {
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- switch (prev_type) {
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- case e_rr_type::CHANX: {
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- draw_chanx_to_chany_edge (prev_node, inode,
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- FROM_X_TO_Y, switch_type, g);
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- break ;
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- }
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- case e_rr_type::CHANY: {
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- draw_chany_to_chany_edge (RRNodeId (prev_node), RRNodeId (inode),
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- switch_type, g);
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- break ;
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- }
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- case e_rr_type::OPIN: {
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- draw_pin_to_chan_edge (prev_node, inode, g);
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-
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- break ;
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- }
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- default : {
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- VPR_ERROR (VPR_ERROR_OTHER,
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- " Unexpected connection from an rr_node of type %d to one of type %d.\n " ,
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- prev_type, rr_type);
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- }
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- }
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- break ;
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- }
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- default : {
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- break ;
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- }
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+ draw_rr_edge (inode, prev_node, draw_state->draw_rr_node [inode].color , g);
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}
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}
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