@@ -2676,7 +2676,7 @@ static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_in
26762676 parse_direct_pin_name (directs[i].from_pin , directs[i].line , &start_pin_index, &end_pin_index, tile_name, port_name);
26772677
26782678 // Figure out which type, port, and pin is used
2679- for (auto & type : device_ctx.physical_tile_types ) {
2679+ for (const auto & type : device_ctx.physical_tile_types ) {
26802680 if (strcmp (type.name , tile_name) == 0 ) {
26812681 physical_tile = &type;
26822682 break ;
@@ -2690,7 +2690,7 @@ static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_in
26902690 clb_to_clb_directs[i].from_clb_type = physical_tile;
26912691
26922692 bool port_found = false ;
2693- for (auto port : physical_tile->ports ) {
2693+ for (const auto & port : physical_tile->ports ) {
26942694 if (0 == strcmp (port.name , port_name)) {
26952695 tile_port = port;
26962696 port_found = true ;
@@ -2716,7 +2716,7 @@ static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_in
27162716 parse_direct_pin_name (directs[i].to_pin , directs[i].line , &start_pin_index, &end_pin_index, tile_name, port_name);
27172717
27182718 // Figure out which type, port, and pin is used
2719- for (auto & type : device_ctx.physical_tile_types ) {
2719+ for (const auto & type : device_ctx.physical_tile_types ) {
27202720 if (strcmp (type.name , tile_name) == 0 ) {
27212721 physical_tile = &type;
27222722 break ;
@@ -2727,10 +2727,10 @@ static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_in
27272727 VPR_THROW (VPR_ERROR_ARCH, " Unable to find block %s.\n " , tile_name);
27282728 }
27292729
2730- clb_to_clb_directs[i].from_clb_type = physical_tile;
2730+ clb_to_clb_directs[i].to_clb_type = physical_tile;
27312731
27322732 port_found = false ;
2733- for (auto port : physical_tile->ports ) {
2733+ for (const auto & port : physical_tile->ports ) {
27342734 if (0 == strcmp (port.name , port_name)) {
27352735 tile_port = port;
27362736 port_found = true ;
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