Merge branch 'master' into placement_search_range

Author: amin1377

.clang-format

@@ -69,6 +69,7 @@ IndentCaseLabels: true
 IndentWidth:     4
 IndentWrappedFunctionNames: false
 IndentPPDirectives: None
+InsertNewlineAtEOF: true
 JavaScriptQuotes: Leave
 JavaScriptWrapImports: true
 KeepEmptyLinesAtTheStartOfBlocks: true

.github/workflows/stale.yml

@@ -0,0 +1,31 @@
+name: 'Close Stale Issues'
+on:
+  schedule:
+    # Run everyday at 1 PM UTC
+    - cron: '0 13 * * *'
+
+jobs:
+  stale:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/stale@v9
+        with:
+          # The message to be shown for stale issues
+          stale-issue-message: 'This issue has been inactive for a year and has been marked as stale. It will be closed in 15 days if it continues to be stale. If you believe this is still an issue, please add a comment.'
+          close-issue-message: 'This issue has been marked stale for 15 days and has been automatically closed.'
+          # If you want to exempt an issue from being marked stale/deleted, label it as 'no-stale'
+          exempt-issue-labels: 'no-stale'
+          days-before-issue-stale: 365
+          days-before-issue-close: 15
+          # Start from the oldest issues
+          ascending: true
+          
+          # The configuration below can be used to allow the same behaviour with PRs.
+          # Since we currently don't want to close old PRs, it is commented out but 
+          # left here in case we change our mind.
+
+          # stale-pr-message: 'This PR has been inactive for a year and has been marked as stale. It will be closed in 15 days if it continues to be stale. If you are still working on this PR, please add a comment.'
+          # close-pr-message: 'This PR has been marked stale for 15 days and has been automatically closed.'
+          # exempt-pr-labels: 'no-stale'
+          # days-before-pr-stale: 365
+          # days-before-pr-close: 15

CONTRIBUTING.md

@@ -77,7 +77,7 @@ This information helps us to quickly reproduce (and hopefully fix) the issue:
 
     Tell us what version of VTR you are using (e.g. the output of `vpr --version`), which Operating System and compiler you are using, or any other relevant information about where or how you are building/running VTR.
 
-Once you've gathered all the information [open an Issue](https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/new?template=bug_report.md) on our issue tracker.
+Once you've gathered all the information [open an Issue](https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/new?template=bug_report.md) on our issue tracker. Issues that do not have any activity for a year will be automatically marked as stale and will be closed after 15 days of being marked as stale.
 
 If you know how to fix the issue, or already have it coded-up, please also consider [submitting the fix](#submitting-code-to-vtr).
 This is likely the fastest way to get bugs fixed!

Makefile

@@ -48,14 +48,14 @@ ifeq ($(VERBOSE),1)
 override CMAKE_PARAMS := -DVTR_ENABLE_VERBOSE=on ${CMAKE_PARAMS}
 endif
 
-# -s : Suppresss makefile output (e.g. entering/leaving directories)
+# -s : Suppresses makefile output (e.g. entering/leaving directories)
 # --output-sync target : For parallel compilation ensure output for each target is synchronized (make version >= 4.0)
 MAKEFLAGS := -s
 
 SOURCE_DIR := $(PWD)
 BUILD_DIR ?= build
 
-#Check for the cmake exectuable
+#Check for the cmake executable
 CMAKE := $(shell command -v cmake 2> /dev/null)
 
 #Show test log on failures with 'make test'

doc/src/api/vtrutil/index.rst

@@ -11,4 +11,5 @@ VTRUTIL API
    container_utils
    logging
    geometry
+   parallel
    other

doc/src/api/vtrutil/parallel.rst

@@ -0,0 +1,13 @@
+=====
+Parallel
+=====
+
+vtr_thread_pool
+-------------
+.. doxygenfile:: vtr_thread_pool.h
+   :project: vtr
+   :sections: briefdescription detaileddescription func innernamespace enum
+
+.. doxygenclass:: vtr::thread_pool
+   :project: vtr
+   :members:

doc/src/vpr/command_line_usage.rst

@@ -379,6 +379,14 @@ Use the options below to override this default naming behaviour.
 
     .. seealso:: :ref:`Routing Resource XML File <vpr_route_resource_file>`.
 
+.. option:: --read_rr_edge_override <file>
+
+    Reads a file that overrides the intrinsic delay of specific edges in RR graph.
+
+    This option should be used with both :option:`--read_rr_graph` and :option:`--write_rr_graph`. When used this way,
+    VPR reads the RR graph, updates the delays of selected edges using :option:`--read_rr_edge_override`,
+    and writes the updated RR graph. The modified RR graph can then be used in later VPR runs.
+
 .. option:: --read_vpr_constraints <file>
 
     Reads the :ref:`VPR constraints <vpr_constraints>` that the flow must respect from the specified XML file.
@@ -1214,7 +1222,7 @@ Analytical Placement is generally split into three stages:
       Uses the legalized solution as anchor-points to pull the solution to a
       more legal solution (similar to the approach from SimPL :cite:`Kim2013_SimPL`).
 
-    **Default:** ``qp-hybrid``
+    **Default:** ``lp-b2b``
 
 .. option:: --ap_partial_legalizer {bipartitioning | flow-based}
 
@@ -1253,6 +1261,15 @@ Analytical Placement is generally split into three stages:
 
     **Default:** ``annealer``
 
+.. option:: --ap_timing_tradeoff <float>
+
+    Controls the trade-off between wirelength (HPWL) and delay minimization in the AP flow.
+
+    A value of 0.0 makes the AP flow focus completely on wirelength minimization,
+    while a value of 1.0 makes the AP flow focus completely on timing optimization.
+
+    **Default:** ``0.5``
+
 .. option:: --ap_verbosity <int>
 
     Controls the verbosity of the AP flow output.

doc/src/vpr/file_formats.rst

@@ -1100,6 +1100,28 @@ To aid in handling large graphs, rr_graph files can also be :ref:`saved in <file
 
 .. _end:
 
+RR Graph Edge Attribute Override File Format (.txt)
+---------------------------------------------------
+This file lets users override attributes of specific edges in the RR graph. Currently, only the intrinsic delay (Tdel)
+can be changed. The expected format is:
+
+.. code-block:: none
+
+    # edge    Tdel
+    64812     5.9e-11
+    9981      4.2e-11
+    1234      7.1e-11
+    4321      9.4e-11
+    (42, 64)  7.3e-11
+
+.. _end:
+
+Lines starting with # are comments and ignored. Each other line should specify either: an edge ID and its new delay, or
+a source/sink node pair and its delay.
+
+This allows more accurate modeling of switch delays in the RR graph without creating many switch types
+in the architecture file and limiting them to small regions. This can be useful for more detailed modeling of
+a fabricated FPGA where layout differences lead to small delay differences in the same type of routing switch.
 
 Network-on-Chip (NoC) Traffic Flows Format (.flows)
 ---------------------------------------------------

libs/EXTERNAL/libcatch2

@@ -126,7 +126,7 @@ struct t_cluster_placement_primitive {
     t_pb_graph_node* pb_graph_node;
     bool valid;
     float base_cost;        /* cost independent of current status of packing */
-    float incremental_cost; /* cost dependant on current status of packing */
+    float incremental_cost; /* cost dependent on current status of packing */
 };
 
 #endif