equivalent: delete physical_tile_type(t_logical_block_type) function

acomodi · acomodi · commit e20ede47b799 · 2019-10-18T13:22:07.000+02:00
Signed-off-by: Alessandro Comodi &lt;acomodi@antmicro.com&gt;
diff --git a/vpr/src/base/SetupGrid.cpp b/vpr/src/base/SetupGrid.cpp
@@ -668,7 +668,7 @@ float calculate_device_utilization(const DeviceGrid& grid, std::map<t_logical_bl
             continue;
         }
 
-        t_physical_tile_type_ptr type = physical_tile_type(kv.first);
+        t_physical_tile_type_ptr type = pick_random_physical_type(kv.first);
 
         size_t count = kv.second;
 
diff --git a/vpr/src/base/check_netlist.cpp b/vpr/src/base/check_netlist.cpp
@@ -91,12 +91,14 @@ static int check_connections_to_global_clb_pins(ClusterNetId net_id, int verbosi
     int global_to_non_global_connection_count = 0;
     for (auto pin_id : cluster_ctx.clb_nlist.net_pins(net_id)) {
         ClusterBlockId blk_id = cluster_ctx.clb_nlist.pin_block(pin_id);
-        int pin_index = cluster_ctx.clb_nlist.pin_physical_index(pin_id);
-
         auto logical_type = cluster_ctx.clb_nlist.block_type(blk_id);
-        auto physical_type = physical_tile_type(logical_type);
+        auto physical_type = pick_random_physical_type(logical_type);
+
+        int log_index = cluster_ctx.clb_nlist.pin_physical_index(pin_id);
+        int pin_index = get_physical_pin(physical_type, logical_type, log_index);
+
         if (physical_type->is_ignored_pin[pin_index] != net_is_ignored
-            && !is_io_type(physical_tile_type(logical_type))) {
+            && !is_io_type(physical_type)) {
             VTR_LOGV_WARN(verbosity > 2,
                           "Global net '%s' connects to non-global architecture pin '%s' (netlist pin '%s')\n",
                           cluster_ctx.clb_nlist.net_name(net_id).c_str(),
diff --git a/vpr/src/base/clustered_netlist.cpp b/vpr/src/base/clustered_netlist.cpp
@@ -52,7 +52,7 @@ int ClusteredNetlist::block_pin_net_index(const ClusterBlockId blk_id, const int
 
 ClusterPinId ClusteredNetlist::block_pin(const ClusterBlockId blk, const int phys_pin_index) const {
     VTR_ASSERT_SAFE(valid_block_id(blk));
-    VTR_ASSERT_SAFE_MSG(phys_pin_index >= 0 && phys_pin_index < physical_tile_type(block_type(blk))->num_pins, "Physical pin index must be in range");
+    VTR_ASSERT_SAFE_MSG(phys_pin_index >= 0 && phys_pin_index < pick_random_physical_type(block_type(blk))->num_pins, "Physical pin index must be in range");
 
     return block_logical_pins_[blk][phys_pin_index];
 }
diff --git a/vpr/src/base/read_netlist.cpp b/vpr/src/base/read_netlist.cpp
@@ -860,7 +860,6 @@ static void load_external_nets_and_cb(ClusteredNetlist& clb_nlist) {
 
     ext_nhash = alloc_hash_table();
 
-    t_physical_tile_type_ptr tile_type;
     t_logical_block_type_ptr block_type;
 
     /* Assumes that complex block pins are ordered inputs, outputs, globals */
@@ -951,43 +950,44 @@ static void load_external_nets_and_cb(ClusteredNetlist& clb_nlist) {
     for (auto blk_id : clb_nlist.blocks()) {
         block_type = clb_nlist.block_type(blk_id);
         // XXX Use pin mapping here! To check that all the possible pins can be used in the correct tile!
-        tile_type = physical_tile_type(block_type);
-        for (j = 0; j < tile_type->num_pins; j++) {
-            //Iterate through each pin of the block, and see if there is a net allocated/used for it
-            clb_net_id = clb_nlist.block_net(blk_id, j);
-
-            if (clb_net_id != ClusterNetId::INVALID()) {
-                //Verify old and new CLB netlists have the same # of pins per net
-                if (RECEIVER == tile_type->class_inf[tile_type->pin_class[j]].type) {
-                    count[clb_net_id]++;
-
-                    if (count[clb_net_id] > (int)clb_nlist.net_sinks(clb_net_id).size()) {
-                        VPR_FATAL_ERROR(VPR_ERROR_NET_F,
-                                        "net %s #%d inconsistency, expected %d terminals but encountered %d terminals, it is likely net terminal is disconnected in netlist file.\n",
-                                        clb_nlist.net_name(clb_net_id).c_str(), size_t(clb_net_id), count[clb_net_id],
-                                        clb_nlist.net_sinks(clb_net_id).size());
-                    }
+        for (const auto& tile_type : block_type->equivalent_tiles) {
+            for (j = 0; j < tile_type->num_pins; j++) {
+                //Iterate through each pin of the block, and see if there is a net allocated/used for it
+                clb_net_id = clb_nlist.block_net(blk_id, j);
 
-                    //Asserts the ClusterBlockId is the same when ClusterNetId & pin BitIndex is provided
-                    VTR_ASSERT(blk_id == clb_nlist.pin_block(*(clb_nlist.net_pins(clb_net_id).begin() + count[clb_net_id])));
-                    //Asserts the block's pin index is the same
-                    VTR_ASSERT(j == clb_nlist.pin_physical_index(*(clb_nlist.net_pins(clb_net_id).begin() + count[clb_net_id])));
-                    VTR_ASSERT(j == clb_nlist.net_pin_physical_index(clb_net_id, count[clb_net_id]));
+                if (clb_net_id != ClusterNetId::INVALID()) {
+                    //Verify old and new CLB netlists have the same # of pins per net
+                    if (RECEIVER == tile_type->class_inf[tile_type->pin_class[j]].type) {
+                        count[clb_net_id]++;
 
-                    // nets connecting to global pins are marked as global nets
-                    if (tile_type->is_pin_global[j]) {
-                        clb_nlist.set_net_is_global(clb_net_id, true);
-                    }
+                        if (count[clb_net_id] > (int)clb_nlist.net_sinks(clb_net_id).size()) {
+                            VPR_FATAL_ERROR(VPR_ERROR_NET_F,
+                                            "net %s #%d inconsistency, expected %d terminals but encountered %d terminals, it is likely net terminal is disconnected in netlist file.\n",
+                                            clb_nlist.net_name(clb_net_id).c_str(), size_t(clb_net_id), count[clb_net_id],
+                                            clb_nlist.net_sinks(clb_net_id).size());
+                        }
 
-                    if (tile_type->is_ignored_pin[j]) {
-                        clb_nlist.set_net_is_ignored(clb_net_id, true);
-                    }
-                    /* Error check performed later to ensure no mixing of ignored and non ignored signals */
+                        //Asserts the ClusterBlockId is the same when ClusterNetId & pin BitIndex is provided
+                        VTR_ASSERT(blk_id == clb_nlist.pin_block(*(clb_nlist.net_pins(clb_net_id).begin() + count[clb_net_id])));
+                        //Asserts the block's pin index is the same
+                        VTR_ASSERT(j == clb_nlist.pin_physical_index(*(clb_nlist.net_pins(clb_net_id).begin() + count[clb_net_id])));
+                        VTR_ASSERT(j == clb_nlist.net_pin_physical_index(clb_net_id, count[clb_net_id]));
 
-                } else {
-                    VTR_ASSERT(DRIVER == tile_type->class_inf[tile_type->pin_class[j]].type);
-                    VTR_ASSERT(j == clb_nlist.pin_physical_index(*(clb_nlist.net_pins(clb_net_id).begin())));
-                    VTR_ASSERT(j == clb_nlist.net_pin_physical_index(clb_net_id, 0));
+                        // nets connecting to global pins are marked as global nets
+                        if (tile_type->is_pin_global[j]) {
+                            clb_nlist.set_net_is_global(clb_net_id, true);
+                        }
+
+                        if (tile_type->is_ignored_pin[j]) {
+                            clb_nlist.set_net_is_ignored(clb_net_id, true);
+                        }
+                        /* Error check performed later to ensure no mixing of ignored and non ignored signals */
+
+                    } else {
+                        VTR_ASSERT(DRIVER == tile_type->class_inf[tile_type->pin_class[j]].type);
+                        VTR_ASSERT(j == clb_nlist.pin_physical_index(*(clb_nlist.net_pins(clb_net_id).begin())));
+                        VTR_ASSERT(j == clb_nlist.net_pin_physical_index(clb_net_id, 0));
+                    }
                 }
             }
         }
@@ -999,8 +999,11 @@ static void load_external_nets_and_cb(ClusteredNetlist& clb_nlist) {
         for (auto pin_id : clb_nlist.net_sinks(net_id)) {
             bool is_ignored_net = clb_nlist.net_is_ignored(net_id);
             block_type = clb_nlist.block_type(clb_nlist.pin_block(pin_id));
-            tile_type = physical_tile_type(block_type);
-            if (tile_type->is_ignored_pin[clb_nlist.pin_physical_index(pin_id)] != is_ignored_net) {
+            auto tile_type = pick_random_physical_type(block_type);
+            int log_pin = clb_nlist.pin_logical_index(pin_id);
+            int phy_pin = get_physical_pin(tile_type, block_type, log_pin);
+
+            if (tile_type->is_ignored_pin[phy_pin] != is_ignored_net) {
                 VTR_LOG_WARN(
                     "Netlist connects net %s to both global and non-global pins.\n",
                     clb_nlist.net_name(net_id).c_str());
diff --git a/vpr/src/base/read_place.cpp b/vpr/src/base/read_place.cpp
@@ -161,7 +161,7 @@ void read_user_pad_loc(const char* pad_loc_file) {
     hash_table = alloc_hash_table();
     for (auto blk_id : cluster_ctx.clb_nlist.blocks()) {
         auto logical_block = cluster_ctx.clb_nlist.block_type(blk_id);
-        if (is_io_type(physical_tile_type(logical_block))) {
+        if (is_io_type(pick_random_physical_type(logical_block))) {
             insert_in_hash_table(hash_table, cluster_ctx.clb_nlist.block_name(blk_id).c_str(), size_t(blk_id));
             place_ctx.block_locs[blk_id].loc.x = OPEN; /* Mark as not seen yet. */
         }
@@ -268,7 +268,7 @@ void read_user_pad_loc(const char* pad_loc_file) {
 
     for (auto blk_id : cluster_ctx.clb_nlist.blocks()) {
         auto logical_block = cluster_ctx.clb_nlist.block_type(blk_id);
-        auto type = physical_tile_type(logical_block);
+        auto type = pick_random_physical_type(logical_block);
         if (is_io_type(type) && place_ctx.block_locs[blk_id].loc.x == OPEN) {
             vpr_throw(VPR_ERROR_PLACE_F, pad_loc_file, 0,
                       "IO block %s location was not specified in the pad file.\n", cluster_ctx.clb_nlist.block_name(blk_id).c_str());
diff --git a/vpr/src/draw/draw.cpp b/vpr/src/draw/draw.cpp
@@ -2730,11 +2730,9 @@ void deselect_all() {
 static void draw_reset_blk_color(ClusterBlockId blk_id) {
     auto& cluster_ctx = g_vpr_ctx.clustering();
 
-    auto logical_block = cluster_ctx.clb_nlist.block_type(blk_id);
-
     t_draw_state* draw_state = get_draw_state_vars();
 
-    draw_state->block_color[blk_id] = get_block_type_color(physical_tile_type(logical_block));
+    draw_state->block_color[blk_id] = get_block_type_color(physical_tile_type(blk_id));
 }
 
 /**
diff --git a/vpr/src/place/initial_placement.cpp b/vpr/src/place/initial_placement.cpp
@@ -273,7 +273,7 @@ static void initial_placement_blocks(int* free_locations, enum e_pad_loc_type pa
             auto logical_block = cluster_ctx.clb_nlist.block_type(blk_id);
 
             /* Don't do IOs if the user specifies IOs; we'll read those locations later. */
-            if (!(is_io_type(physical_tile_type(logical_block)) && pad_loc_type == USER)) {
+            if (!(is_io_type(pick_random_physical_type(logical_block)) && pad_loc_type == USER)) {
                 /* Randomly select a free location of the appropriate type for blk_id.
                  * We have a linearized list of all the free locations that can
                  * accommodate a block of that type in free_locations[itype].
@@ -304,7 +304,7 @@ static void initial_placement_blocks(int* free_locations, enum e_pad_loc_type pa
                 place_ctx.block_locs[blk_id].loc = to;
 
                 //Mark IOs as fixed if specifying a (fixed) random placement
-                if (is_io_type(physical_tile_type(logical_block)) && pad_loc_type == RANDOM) {
+                if (is_io_type(pick_random_physical_type(logical_block)) && pad_loc_type == RANDOM) {
                     place_ctx.block_locs[blk_id].is_fixed = true;
                 }
 
diff --git a/vpr/src/place/uniform_move_generator.cpp b/vpr/src/place/uniform_move_generator.cpp
@@ -18,7 +18,7 @@ e_create_move UniformMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks
 
     t_pl_loc to;
 
-    auto type = pick_random_placement_type(cluster_from_type);
+    auto type = pick_random_physical_type(cluster_from_type);
 
     if (!find_to_loc_uniform(type, rlim, from, to)) {
         return e_create_move::ABORT;
diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp
@@ -1032,10 +1032,7 @@ static vtr::vector<ClusterNetId, std::vector<int>> load_net_rr_terminals(const t
              * are offset to get their actual rr_node */
             node_block_pin = cluster_ctx.clb_nlist.pin_logical_index(pin_id);
 
-            auto pin_directs_map = type->tile_block_pin_directs_map;
-            auto map = pin_directs_map[logical_block->index];
-
-            auto orig_phys_pin = map[t_logical_pin(node_block_pin)].pin;
+            int orig_phys_pin = get_physical_pin(type, logical_block, node_block_pin);
 
             VTR_ASSERT(type->num_pins % type->capacity == 0);
             int max_num_block_pins = type->num_pins / type->capacity;
diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp
@@ -318,7 +318,7 @@ std::vector<AtomPinId> find_clb_pin_connected_atom_pins(ClusterBlockId clb, int
 
     auto logical_block = clb_nlist.block_type(clb);
 
-    if (is_opin(log_pin, physical_tile_type(logical_block))) {
+    if (is_opin(log_pin, pick_random_physical_type(logical_block))) {
         //output
         AtomPinId driver = find_clb_pin_driver_atom_pin(clb, log_pin, pb_gpin_lookup);
         if (driver) {
@@ -624,20 +624,6 @@ bool is_empty_type(t_logical_block_type_ptr type) {
     return type == device_ctx.EMPTY_LOGICAL_BLOCK_TYPE;
 }
 
-t_physical_tile_type_ptr physical_tile_type(t_logical_block_type_ptr logical_block_type) {
-    auto& device_ctx = g_vpr_ctx.device();
-    auto& physical_tiles = device_ctx.physical_tile_types;
-
-    // Loop through the ordered map to get tiles in a decreasing priority order
-    for (auto& physical_tiles_ids : logical_block_type->physical_tiles_priority) {
-        for (auto tile_id : physical_tiles_ids.second) {
-            return &physical_tiles[tile_id];
-        }
-    }
-
-    VPR_THROW(VPR_ERROR_OTHER, "No corresponding physical tile type found for logical block type %s\n", logical_block_type->name);
-}
-
 t_physical_tile_type_ptr physical_tile_type(ClusterBlockId blk) {
     auto& place_ctx = g_vpr_ctx.placement();
     auto& device_ctx = g_vpr_ctx.device();
@@ -2176,7 +2162,7 @@ bool is_tile_compatible(t_physical_tile_type_ptr physical_tile, t_logical_block_
     return std::find(equivalent_tiles.begin(), equivalent_tiles.end(), physical_tile) != equivalent_tiles.end();
 }
 
-t_physical_tile_type_ptr pick_random_placement_type(t_logical_block_type_ptr logical_block) {
+t_physical_tile_type_ptr pick_random_physical_type(t_logical_block_type_ptr logical_block) {
     auto equivalent_tiles = logical_block->equivalent_tiles;
 
     size_t num_equivalent_tiles = equivalent_tiles.size();
@@ -2189,6 +2175,44 @@ t_physical_tile_type_ptr pick_random_placement_type(t_logical_block_type_ptr log
     return equivalent_tiles[index];
 }
 
+int get_logical_pin(t_physical_tile_type_ptr physical_tile,
+                    t_logical_block_type_ptr logical_block,
+                    int pin) {
+    t_physical_pin physical_pin(pin);
+
+    auto direct_map = physical_tile->tile_block_pin_directs_map.at(logical_block->index);
+    auto result = direct_map.find(physical_pin);
+
+    if (result == direct_map.inverse_end()) {
+        VTR_LOG_WARN(
+            "Couldn't find the corresponding logical pin of the physical pin %d."
+            "Physical Tile: %s, Logical Block: %s.\n",
+            pin, physical_tile->name, logical_block->name);
+        return OPEN;
+    }
+
+    return result->second.pin;
+}
+
+int get_physical_pin(t_physical_tile_type_ptr physical_tile,
+                     t_logical_block_type_ptr logical_block,
+                     int pin) {
+    t_logical_pin logical_pin(pin);
+
+    auto direct_map = physical_tile->tile_block_pin_directs_map.at(logical_block->index);
+    auto result = direct_map.find(logical_pin);
+
+    if (result == direct_map.end()) {
+        VTR_LOG_WARN(
+            "Couldn't find the corresponding physical pin of the logical pin %d."
+            "Physical Tile: %s, Logical Block: %s.\n",
+            pin, physical_tile->name, logical_block->name);
+        return OPEN;
+    }
+
+    return result->second.pin;
+}
+
 void pretty_print_uint(const char* prefix, size_t value, int num_digits, int scientific_precision) {
     //Print as integer if it will fit in the width, other wise scientific
     if (value <= std::pow(10, num_digits) - 1) {
diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h
@@ -29,7 +29,6 @@ bool is_empty_type(t_physical_tile_type_ptr type);
 bool is_empty_type(t_logical_block_type_ptr type);
 
 //Returns the corresponding physical/logical type given the logical/physical type as parameter
-t_physical_tile_type_ptr physical_tile_type(t_logical_block_type_ptr logical_block_type);
 t_physical_tile_type_ptr physical_tile_type(ClusterBlockId blk);
 t_logical_block_type_ptr logical_block_type(t_physical_tile_type_ptr physical_tile_type);
 
@@ -172,7 +171,14 @@ void place_sync_external_block_connections(ClusterBlockId iblk);
 int get_max_num_pins(t_logical_block_type_ptr logical_block);
 
 bool is_tile_compatible(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block);
-t_physical_tile_type_ptr pick_random_placement_type(t_logical_block_type_ptr logical_block);
+t_physical_tile_type_ptr pick_random_physical_type(t_logical_block_type_ptr logical_block);
+
+int get_logical_pin(t_physical_tile_type_ptr physical_tile,
+                    t_logical_block_type_ptr logical_block,
+                    int pin);
+int get_physical_pin(t_physical_tile_type_ptr physical_tile,
+                     t_logical_block_type_ptr logical_block,
+                     int pin);
 
 int max_pins_per_grid_tile();
 

Original file line number	Diff line number	Diff line change
`@@ -668,7 +668,7 @@ float calculate_device_utilization(const DeviceGrid& grid, std::map<t_logical_bl`
`668`	`668`	`continue;`
`669`	`669`	`}`
`670`	`670`
`671`		`- t_physical_tile_type_ptr type = physical_tile_type(kv.first);`
	`671`	`+ t_physical_tile_type_ptr type = pick_random_physical_type(kv.first);`
`672`	`672`
`673`	`673`	`size_t count = kv.second;`
`674`	`674`
Original file line number	Diff line number	Diff line change
`@@ -52,7 +52,7 @@ int ClusteredNetlist::block_pin_net_index(const ClusterBlockId blk_id, const int`
`52`	`52`
`53`	`53`	`ClusterPinId ClusteredNetlist::block_pin(const ClusterBlockId blk, const int phys_pin_index) const {`
`54`	`54`	`VTR_ASSERT_SAFE(valid_block_id(blk));`
`55`		`- VTR_ASSERT_SAFE_MSG(phys_pin_index >= 0 && phys_pin_index < physical_tile_type(block_type(blk))->num_pins, "Physical pin index must be in range");`
	`55`	`+ VTR_ASSERT_SAFE_MSG(phys_pin_index >= 0 && phys_pin_index < pick_random_physical_type(block_type(blk))->num_pins, "Physical pin index must be in range");`
`56`	`56`
`57`	`57`	`return block_logical_pins_[blk][phys_pin_index];`
`58`	`58`	`}`