Closed
Description
Proposed Behaviour
It is possible that a single logical block type could be mapped to multiple potential physical grid tiles in the FPGA.
Examples of this include
- IO types associated with different locations (e.g. IO_LEFT, IO_RIGHT, IO_TOP, IO_BOTTOM)
- LUTRAM (CLBL/CLBM, LAB/MLAB)
In general it should be possible to list a set of equivalent placement locations/sites for each block type.
Current Behaviour
VPR assumes that each top-level pb_type
can only be placed at a placement location of exactly the same type.
Possible Solution
We should probably decouple the packing decisions (i.e. logical block types exist and can be created), from the placer's decisions (what grid tiles the logical block types can be placed in).
Currently there is no distinction.
Context
This will help improve the generality of the flow.
It will also fix non-intuitive/confusing behaviour such as #268, #512, #349.