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Fix apostrophe parser in AUTOWIRE (#1854) (#1855).
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* verilog-mode.el (verilog-read-sub-decls-expr):
Fix apostrophe parser in AUTOWIRE (#1854) (#1855).
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dong authored and wsnyder committed Jan 11, 2024
1 parent 21a1000 commit 2a4294c
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33 changes: 33 additions & 0 deletions tests/autowire_apostrophe.sv
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module test_port0
(/*AUTOARG*/);
output [31:0] d[2];
endmodule // test_port

module test_port1
(/*AUTOARG*/);
input [31:0] dd[2];
endmodule // test_port1

module top()
/*AUTOWIRE*/

/*
test_port0 AUTO_TEMPLATE
(
.d\(.*\) ('{d_1\1[],d_2\1[]}),
);
*/
test_port0
u0(/*AUTOINST*/);

/*
test_port1 AUTO_TEMPLATE
(
.d\(.*\) ('{d_1\1[],d_2\1[]}),
);
*/

test_port1
u1(/*AUTOINST*/);

endmodule // top
47 changes: 47 additions & 0 deletions tests_ok/autowire_apostrophe.sv
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module test_port0
(/*AUTOARG*/
// Outputs
d
);
output [31:0] d[2];
endmodule // test_port

module test_port1
(/*AUTOARG*/
// Inputs
dd
);
input [31:0] dd[2];
endmodule // test_port1

module top()
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] d_1; // From u0 of test_port0.v
wire [31:0] d_2; // From u0 of test_port0.v
// End of automatics

/*
test_port0 AUTO_TEMPLATE
(
.d\(.*\) ('{d_1\1[],d_2\1[]}),
);
*/
test_port0
u0(/*AUTOINST*/
// Outputs
.d ('{d_1[31:0],d_2[31:0]})); // Templated

/*
test_port1 AUTO_TEMPLATE
(
.d\(.*\) ('{d_1\1[],d_2\1[]}),
);
*/

test_port1
u1(/*AUTOINST*/
// Inputs
.dd ('{d_1d[31:0],d_2d[31:0]})); // Templated

endmodule // top
2 changes: 1 addition & 1 deletion verilog-mode.el
Original file line number Diff line number Diff line change
Expand Up @@ -9680,7 +9680,7 @@ Return an array of [outputs inouts inputs wire reg assign const gparam intf]."
(cond
;; {..., a, b} requires us to recurse on a,b
;; To support {#{},{#{a,b}} we'll just split everything on [{},]
((string-match "^\\s-*{\\(.*\\)}\\s-*$" expr)
((string-match "^\\s-*'?{\\(.*\\)}\\s-*$" expr)
(let ((mlst (split-string (match-string 1 expr) "[{},]"))
mstr)
(while (setq mstr (pop mlst))
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