From 2a4294c28fa5eef84df84b04e4d53cacc0644ae6 Mon Sep 17 00:00:00 2001
From: dong <dong@debian>
Date: Wed, 10 Jan 2024 19:29:08 -0500
Subject: [PATCH] Fix apostrophe parser in AUTOWIRE (#1854) (#1855).

* verilog-mode.el (verilog-read-sub-decls-expr):
Fix apostrophe parser in AUTOWIRE (#1854) (#1855).
---
 tests/autowire_apostrophe.sv    | 33 +++++++++++++++++++++++
 tests_ok/autowire_apostrophe.sv | 47 +++++++++++++++++++++++++++++++++
 verilog-mode.el                 |  2 +-
 3 files changed, 81 insertions(+), 1 deletion(-)
 create mode 100644 tests/autowire_apostrophe.sv
 create mode 100644 tests_ok/autowire_apostrophe.sv

diff --git a/tests/autowire_apostrophe.sv b/tests/autowire_apostrophe.sv
new file mode 100644
index 0000000..2fc973f
--- /dev/null
+++ b/tests/autowire_apostrophe.sv
@@ -0,0 +1,33 @@
+module test_port0
+(/*AUTOARG*/);
+    output [31:0] d[2];
+endmodule // test_port
+
+module test_port1
+(/*AUTOARG*/);
+   input [31:0] dd[2];
+endmodule // test_port1
+
+module top()
+/*AUTOWIRE*/
+
+/*
+   test_port0  AUTO_TEMPLATE
+   (
+   .d\(.*\)         ('{d_1\1[],d_2\1[]}),
+   );
+*/
+test_port0
+  u0(/*AUTOINST*/);
+
+  /*
+   test_port1  AUTO_TEMPLATE
+   (
+   .d\(.*\)         ('{d_1\1[],d_2\1[]}),
+   );
+*/
+
+test_port1
+  u1(/*AUTOINST*/);
+
+endmodule // top
diff --git a/tests_ok/autowire_apostrophe.sv b/tests_ok/autowire_apostrophe.sv
new file mode 100644
index 0000000..1ced274
--- /dev/null
+++ b/tests_ok/autowire_apostrophe.sv
@@ -0,0 +1,47 @@
+module test_port0
+  (/*AUTOARG*/
+   // Outputs
+   d
+   );
+   output [31:0] d[2];
+endmodule // test_port
+
+module test_port1
+  (/*AUTOARG*/
+   // Inputs
+   dd
+   );
+   input [31:0] dd[2];
+endmodule // test_port1
+
+module top()
+  /*AUTOWIRE*/
+  // Beginning of automatic wires (for undeclared instantiated-module outputs)
+  wire [31:0] d_1; // From u0 of test_port0.v
+   wire [31:0] d_2; // From u0 of test_port0.v
+   // End of automatics
+   
+   /*
+    test_port0  AUTO_TEMPLATE
+    (
+    .d\(.*\)         ('{d_1\1[],d_2\1[]}),
+    );
+    */
+   test_port0
+     u0(/*AUTOINST*/
+        // Outputs
+        .d                                      ('{d_1[31:0],d_2[31:0]})); // Templated
+   
+   /*
+    test_port1  AUTO_TEMPLATE
+    (
+    .d\(.*\)         ('{d_1\1[],d_2\1[]}),
+    );
+    */
+   
+   test_port1
+     u1(/*AUTOINST*/
+        // Inputs
+        .dd                             ('{d_1d[31:0],d_2d[31:0]})); // Templated
+   
+endmodule // top
diff --git a/verilog-mode.el b/verilog-mode.el
index 4238132..4e6448f 100644
--- a/verilog-mode.el
+++ b/verilog-mode.el
@@ -9680,7 +9680,7 @@ Return an array of [outputs inouts inputs wire reg assign const gparam intf]."
   (cond
    ;; {..., a, b} requires us to recurse on a,b
    ;; To support {#{},{#{a,b}} we'll just split everything on [{},]
-   ((string-match "^\\s-*{\\(.*\\)}\\s-*$" expr)
+   ((string-match "^\\s-*'?{\\(.*\\)}\\s-*$" expr)
     (let ((mlst (split-string (match-string 1 expr) "[{},]"))
           mstr)
       (while (setq mstr (pop mlst))