Description
Author Name: Dan Hopper
Original Redmine Issue: 1257 from https://www.veripool.org
There's an interesting difference in indentation in the below example module. The assign statement after an always block within a generate construct will be correctly indented if it's within a generate region (explicit generate/endgenerate lines), and incorrectly indented if the optional generate region (generate/endgenerate) is omitted.
If you load the below snippet in and reformat, the commented assign statement will be (incorrectly) indented to column 0. If you remove the comments on the generate/endgenerate pairs, it will indent properly. According to SV 1800-2012, the generate/endgenerate pair is optional, so ideally it would treat both versions identically.
I'm not proficient in Lisp so it wasn't immediately obvious to me how to fix the .el file to eliminate.
This occurs with verilog-mode-2017-12-21-39c77b2-vpo.el and also at least as far back as verilog-mode-842.el.
Thanks,
Dan
module t1
(
);
genvar pipe;
logic [1:0] v;
logic x;
//generate
for (pipe=0; pipe<2; pipe++) begin : v_bl
always_comb begin
assign v[pipe] = '0;
end
assign x = '0; // will be incorrectly indented to column 0
end
//endgenerate
endmodule