Commentary

Author: wsnyder

README.pod

@@ -202,10 +202,7 @@ writing a parser from scratch).
 The Verilator program also contains a very similar front end as
 Verilog-Perl and can create XML output showing the abstract syntax tree.
 Verilator also understands how to elaborate and connect complex pins and
-types, but supports mostly only the synthesis subset of SystemVerilog.
-
-If you're looking to parse only synthesizable code this is the recommended
-route.
+types, but supports a subset of SystemVerilog.
 
 =item Verilog-Mode for Emacs
 
@@ -215,6 +212,34 @@ a better solution to this problem, as it results in completely portable
 code; the program (Verilog-Mode) isn't needed for others to update the
 design.  It's also in very common usage, including by many IP providers.
 
+=item slang
+
+SystemVerilog Language Services (slang) L<https://sv-lang.com> provides
+various components for lexing, parsing, type checking, and elaborating
+SystemVerilog code.  It's fast and supports UVM.
+
+=item Surelog
+
+Surelog L<https://github.com/chipsalliance/Surelog> is a SystemVerilog 2017
+Pre-processor, Parser, Elaborator, and UHDM Compiler. It handles UVM and
+provides an IEEE Design/TB C/C++ VPI and Python AST API.
+
+=item SV-Parser
+
+Sv-parser L<https://github.com/dalance/sv-parser> is a SystemVerilog parser
+library fully compliant with IEEE 1800-2017.  that returns a concrete
+syntax tree.
+
+=item Tree-Sitter-Verilog
+
+Tree-Sitter-Verilog L<https://github.com/tree-sitter/tree-sitter-verilog>
+is a verilog grammar for the JavaScript tree-sitter parser.
+
+=item Verible
+
+Verible L<https://github.com/chipsalliance/verible> parses IEEE 1800-2017,
+with the ability to parse un-preprocessed source files.
+
 =back
 
 =head1 INSTALLATION