[BUG REPORT] Construction of half and full adder using XOR and NAND gates and verification of its operation

[vlabs-bug]

Bug Reported on Tuesday 25 February, 2025 at 5:09:29 pm IST in

Lab - Digital Electronics IITR
Experiment - Construction of half and full adder using XOR and NAND gates and verification of its operation

Type(s) of Issue -

• Content Not Visible
• Page Not Loading
• Insufficient Content
• Incorrect Content

Additional info- 123456789

UserAgent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:135.0) Gecko/20100101 Firefox/135.0

User System Information -
Browser Name: Firefox
Browser Version: 135.0
OS Name: Windows
OS Version: 10

Experiment Link - https://de-iitr.vlabs.ac.in/exp/half-full-adder/theory.html

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  Following information is strictly meant for machine use. Please do not edit:

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