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1 parent 090c8da commit 74664b5Copy full SHA for 74664b5
vlib/v/gen/native/expr.v
@@ -64,7 +64,7 @@ fn (mut g Gen) expr(node ast.Expr) {
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ast.IntegerLiteral {
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// Integer literal stores both signed and unsigned integers, some unsigned integers are too big for i64 but not for u64
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println(node.val)
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- if node.val[0] == `-` { // if the number is negative
+ if node.val.len > 0 && node.val[0] == `-` { // if the number is negative
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g.code_gen.mov64(g.code_gen.main_reg(), node.val.i64())
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} else {
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g.code_gen.mov64u(g.code_gen.main_reg(), node.val.u64())
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