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test_gpu_shift.cpp
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#if defined(USE_CUDA)
#include <gtest/gtest.h>
#include <torch/csrc/jit/codegen/cuda/arith.h>
#include <torch/csrc/jit/codegen/cuda/codegen.h>
#include <torch/csrc/jit/codegen/cuda/disjoint_set.h>
#include <torch/csrc/jit/codegen/cuda/executor.h>
#include <torch/csrc/jit/codegen/cuda/executor_launch_params.h>
#include <torch/csrc/jit/codegen/cuda/expr_evaluator.h>
#include <torch/csrc/jit/codegen/cuda/fusion.h>
#include <torch/csrc/jit/codegen/cuda/fusion_segmenter.h>
#include <torch/csrc/jit/codegen/cuda/interface.h>
#include <torch/csrc/jit/codegen/cuda/ir_all_nodes.h>
#include <torch/csrc/jit/codegen/cuda/ir_builder.h>
#include <torch/csrc/jit/codegen/cuda/ir_graphviz.h>
#include <torch/csrc/jit/codegen/cuda/ir_iostream.h>
#include <torch/csrc/jit/codegen/cuda/ir_utils.h>
#include <torch/csrc/jit/codegen/cuda/iter_visitor.h>
#include <torch/csrc/jit/codegen/cuda/kernel_cache.h>
#include <torch/csrc/jit/codegen/cuda/kernel_expr_evaluator.h>
#include <torch/csrc/jit/codegen/cuda/kernel_ir.h>
#include <torch/csrc/jit/codegen/cuda/lower2device.h>
#include <torch/csrc/jit/codegen/cuda/mutator.h>
#include <torch/csrc/jit/codegen/cuda/root_domain_map.h>
#include <torch/csrc/jit/codegen/cuda/scheduler/all_schedulers.h>
#include <torch/csrc/jit/codegen/cuda/scheduler/utils.h>
#include <torch/csrc/jit/codegen/cuda/transform_replay.h>
#include <torch/csrc/jit/codegen/cuda/transform_rfactor.h>
// fuser and IR parser
#include "test_gpu_validator.h"
#include <ATen/cuda/CUDAContext.h>
#include <ATen/cuda/Exceptions.h>
#include <c10/cuda/CUDAStream.h>
#include <algorithm>
#include <iostream>
// Tests go in torch::jit
namespace torch {
namespace jit {
using namespace torch::jit::fuser::cuda;
using namespace at::indexing;
namespace {
// Make a tensor that is known to be fully contiguous of dimensionality=ndims,
// but unknown sizes
TensorView* makeContigTensor(size_t ndims, DataType dtype = DataType::Float) {
return TensorViewBuilder()
.ndims(ndims)
.dtype(dtype)
.contiguity(std::vector<bool>(ndims, true))
.build();
}
// Make a tensor that is known to be non-contiguous of dimensionality=ndims,
// but unknown sizes
TensorView* makeSymbolicTensor(size_t ndims, DataType dtype = DataType::Float) {
return TensorViewBuilder().ndims(ndims).dtype(dtype).build();
}
// Make a non-contiguous tensor of compile-time known sizes
TensorView* makeConcreteTensor(
std::vector<int64_t> shape,
DataType dtype = DataType::Float) {
return TensorViewBuilder().shape(shape).dtype(dtype).build();
}
void checkIntValue(
ExpressionEvaluator& evaluator,
Val* val,
Int::ScalarType expected_value) {
TORCH_CHECK(val->isAnInt());
const auto actual_value = evaluator.evaluate(val);
TORCH_CHECK(actual_value.has_value());
TORCH_CHECK(actual_value.value() == expected_value);
}
void checkIntValue(
kir::ExpressionEvaluator& evaluator,
const Val* val,
Int::ScalarType expected_value) {
const auto actual_value = evaluator.evaluate(val);
TORCH_CHECK(actual_value.has_value());
TORCH_CHECK(actual_value.value() == expected_value);
}
// Used to signify invalid ranges, i.e., values at offset 0 to
// start_offset, and values at offset stop_offset to the end of the
// domain.
static constexpr int invalid_marker = 1;
// ATen version of tensor shifting
auto shift(
at::Tensor tensor,
const std::vector<int>& offsets,
std::vector<int> padding = {}) {
TORCH_INTERNAL_ASSERT(tensor.ndimension() == offsets.size());
if (padding.empty()) {
padding = offsets;
for (auto& p : padding) {
p = std::abs(p);
}
}
at::Tensor t = tensor;
for (size_t i = 0; i < offsets.size(); ++i) {
auto offset = offsets[i];
t = t.roll(offsets[i], i);
if (offset == 0) {
continue;
}
// Zero padding
std::vector<at::indexing::TensorIndex> indices(
tensor.ndimension(), at::indexing::Slice(0, at::indexing::None));
if (offset > 0) {
indices[i] = at::indexing::Slice(0, offset);
} else {
indices[i] = at::indexing::Slice(offset, at::indexing::None);
}
t.index(indices) = 0;
// Fill the outside range by the special marker value.
const auto pad = padding[i];
if (offset > 0) {
indices[i] = at::indexing::Slice(0, offset - pad);
} else {
offset += pad;
TORCH_INTERNAL_ASSERT(offset <= 0);
if (offset == 0) {
continue;
}
indices[i] = at::indexing::Slice(offset, at::indexing::None);
}
t.index(indices) = invalid_marker;
}
return t;
}
// ATen version of tensor gather
auto gather(
at::Tensor tensor,
const std::vector<int>& window_shape,
const std::vector<std::vector<int>>& pad_width,
std::vector<int> strides = {}) {
TORCH_CHECK(
tensor.ndimension() == window_shape.size(),
"Invalid window shape: ",
window_shape,
". Size of the window shape is different from the tensor dimension.");
TORCH_CHECK(
tensor.ndimension() == pad_width.size(),
"Invalid pad width: ",
pad_width,
". Size of the pad width is different from the tensor dimension.");
if (strides.empty()) {
strides = std::vector<int>(tensor.ndimension(), 1);
} else {
TORCH_CHECK(
tensor.ndimension() == strides.size(),
"Invalid strides: ",
strides,
". Size of strides is different from the tensor dimension.");
}
at::Tensor t = tensor;
for (size_t i = 0; i < window_shape.size(); ++i) {
const auto w_size = window_shape[i];
TORCH_CHECK(w_size != 0);
const auto& pad = pad_width[i];
TORCH_CHECK(pad.size() == 2);
const auto out_extent_adj = -w_size + 1 + pad[0] + pad[1];
TORCH_INTERNAL_ASSERT(out_extent_adj <= 0);
const auto stride = strides[i];
TORCH_CHECK(stride >= 1);
at::Tensor concat_tensor;
for (int w = 0; w < w_size; ++w) {
std::vector<int> shift_offsets(t.ndimension(), 0);
shift_offsets[i] = pad[0] - w;
auto shifted = shift(t, shift_offsets);
// Apply stride
if (stride != 1) {
std::vector<at::indexing::TensorIndex> indices(
shifted.ndimension(), at::indexing::Slice(0, at::indexing::None));
if (out_extent_adj == 0) {
indices[i] = at::indexing::Slice(0, at::indexing::None, strides[i]);
} else {
indices[i] = at::indexing::Slice(0, out_extent_adj, strides[i]);
}
shifted = shifted.index(indices);
}
shifted = shifted.unsqueeze(-1);
if (w == 0) {
concat_tensor = shifted;
} else {
concat_tensor = at::cat({concat_tensor, shifted}, -1);
}
}
t = concat_tensor;
}
// Fill invalid regions with the marker. Note that when non-unit
// stride is used, it trims invalid regions, so no marking is
// necessary.
for (size_t i = 0; i < window_shape.size(); ++i) {
if (strides[i] != 1) {
continue;
}
const auto out_extent_adj =
-window_shape[i] + 1 + pad_width[i][0] + pad_width[i][1];
if (out_extent_adj < 0) {
std::vector<at::indexing::TensorIndex> indices(
t.ndimension(), at::indexing::Slice(0, at::indexing::None));
indices[i] = at::indexing::Slice(out_extent_adj, at::indexing::None);
t.index(indices) = invalid_marker;
}
}
return t;
}
} // namespace
// Shift an input tensor
TEST_F(NVFuserTest, FusionShift1_CUDA) {
Fusion fusion;
FusionGuard fg(&fusion);
auto tv0 = makeSymbolicTensor(2);
fusion.addInput(tv0);
auto tv1 = shift(tv0, {-1, 0});
fusion.addOutput(tv1);
auto tv2 = shift(tv0, {0, 1});
fusion.addOutput(tv2);
auto tv3 = shift(tv0, {2, 2});
fusion.addOutput(tv3);
auto tv4 = shift(tv0, {-2, -2});
fusion.addOutput(tv4);
int numel_x = 9;
int numel_y = 11;
auto options = at::TensorOptions().dtype(at::kFloat).device(at::kCUDA, 0);
at::Tensor t0 = at::randn({numel_x, numel_y}, options);
std::vector<IValue> inputs = {t0};
FusionExecutor fe;
fe.compileFusion(&fusion, inputs);
auto outputs = fe.runFusion(inputs);
auto t1 = shift(t0, {-1, 0});
TORCH_CHECK(t1.equal(outputs[0]));
auto t2 = shift(t0, {0, 1});
TORCH_CHECK(t2.equal(outputs[1]));
auto t3 = shift(t0, {2, 2});
TORCH_CHECK(t3.equal(outputs[2]));
auto t4 = shift(t0, {-2, -2});
TORCH_CHECK(t4.equal(outputs[3]));
}
// Shifts an intermediate tensor
TEST_F(NVFuserTest, FusionShift2_CUDA) {
Fusion fusion;
FusionGuard fg(&fusion);
auto tv0 = makeSymbolicTensor(2);
fusion.addInput(tv0);
auto tv1 = add(tv0, IrBuilder::create<Double>(1));
auto tv2 = shift(tv1, {-1, 0});
fusion.addOutput(tv2);
// make it a little more complex
auto tv3 = add(tv0, IrBuilder::create<Double>(3));
auto tv4 = add(tv3, IrBuilder::create<Double>(4));
auto tv5 = shift(tv4, {-1, 0});
auto tv6 = shift(tv4, {0, -1});
auto tv7 = shift(tv4, {1, 0});
auto tv8 = shift(tv4, {0, 0});
auto tv9 = add(tv5, tv6);
auto tv10 = add(tv9, tv7);
auto tv11 = add(tv10, tv8);
fusion.addOutput(tv11);
for (auto tv : {tv1, tv2, tv3, tv4, tv5, tv6, tv7, tv8, tv9, tv10, tv11}) {
tv->setMemoryType(MemoryType::Global);
}
// t1 allocation: (t1.size[0] + 1) * (t1.size[1])
// t3 allocation: (t3.size[0] + 2) * (t3.size[1] + 1)
// t4 allocation: (t3.size[0] + 2) * (t3.size[1] + 1)
GpuLower gpulw(&fusion);
for (const auto expr : gpulw.kernel()->unordered_exprs()) {
if (auto alloc = dynamic_cast<kir::Allocate*>(expr)) {
auto tensor_name = alloc->buffer()->name();
if (tensor_name == 1 || tensor_name == 3 || tensor_name == 4) {
TORCH_CHECK(alloc->shape().size() == 2);
for (int i = 0; i < 2; ++i) {
if (tensor_name == 1 && i == 1) {
TORCH_CHECK(alloc->shape().at(i)->isA<NamedScalar>());
continue;
}
auto def =
dynamic_cast<BinaryOp*>(alloc->shape().at(i)->definition());
TORCH_CHECK(
def != nullptr && def->getBinaryOpType() == BinaryOpType::Add);
TORCH_CHECK(def->as<BinaryOp>()->lhs()->isA<NamedScalar>());
auto rhs = dynamic_cast<Int*>(def->as<BinaryOp>()->rhs());
TORCH_CHECK(rhs != nullptr && rhs->isConst());
int rhs_value = *rhs->value();
if (tensor_name == 1) {
TORCH_CHECK(i == 0);
TORCH_CHECK(rhs_value == 1);
} else {
if (i == 0) {
TORCH_CHECK(rhs_value == 2);
} else {
TORCH_CHECK(rhs_value == 1);
}
}
}
}
}
}
int numel_x = 9;
int numel_y = 11;
auto options = at::TensorOptions().dtype(at::kFloat).device(at::kCUDA, 0);
at::Tensor t0 = at::randn({numel_x, numel_y}, options);
std::vector<IValue> inputs = {t0};
FusionExecutor fe;
fe.compileFusion(&fusion, inputs);
auto outputs = fe.runFusion(inputs);
auto t1 = t0 + 1;
auto t2 = shift(t1, {-1, 0});
auto t3 = t0 + 3;
auto t4 = t3 + 4;
auto t5 = shift(t4, {-1, 0});
auto t6 = shift(t4, {0, -1});
auto t7 = shift(t4, {1, 0});
auto t8 = shift(t4, {0, 0});
auto t9 = t5 + t6;
auto t10 = t9 + t7;
auto t11 = t10 + t8;
testValidate(&fusion, outputs, inputs, {t2, t11}, __LINE__, __FILE__);
}
TEST_F(NVFuserTest, FusionShiftRightOfCA_CUDA) {
Fusion fusion;
FusionGuard fg(&fusion);
auto tv0 = makeSymbolicTensor(2);
fusion.addInput(tv0);
auto tv1 = add(tv0, IrBuilder::create<Double>(1));
auto tv2 = shift(tv1, {0, 1});
fusion.addOutput(tv2);
tv0->computeAt(tv2, -2);
tv1->setMemoryType(MemoryType::Global);
int numel_x = 100;
int numel_y = 101;
auto options = at::TensorOptions().dtype(at::kFloat).device(at::kCUDA, 0);
at::Tensor t0 = at::randn({numel_x, numel_y}, options);
std::vector<IValue> inputs = {t0};
FusionExecutor fe;
fe.compileFusion(&fusion, inputs);
auto outputs = fe.runFusion(inputs);
auto t1 = t0 + 1;
auto t2 = shift(t1, {0, 1});
TORCH_CHECK(t2.allclose(outputs[0]));
}
TEST_F(NVFuserTest, FusionShiftLeftOfCA_CUDA) {
Fusion fusion;
FusionGuard fg(&fusion);
auto tv0 = makeSymbolicTensor(2);
fusion.addInput(tv0);
auto tv1 = add(tv0, IrBuilder::create<Double>(1));
auto tv2 = add(tv1, IrBuilder::create<Double>(1));
auto tv3 = shift(tv2, {-1, 0});
auto tv4 = add(tv3, IrBuilder::create<Double>(1));
fusion.addOutput(tv4);
tv0->computeAt(tv4, -1);
// Lowering should trigger an assertion failure as a shifted axis is
// found inside an allocation position.
ASSERT_ANY_THROW(fusion.printKernel());
}
TEST_F(NVFuserTest, FusionShiftSplit1_CUDA) {
Fusion fusion;
FusionGuard fg(&fusion);
auto tv0 = makeSymbolicTensor(2);
fusion.addInput(tv0);
auto tv1 = add(tv0, IrBuilder::create<Double>(1));
auto tv2 = shift(tv1, {0, 1});
auto tv3 = shift(tv1, {0, -2});
fusion.addOutput(tv2);
fusion.addOutput(tv3);
int split_factor = 4;
tv2->split(-1, split_factor);
tv3->split(-1, split_factor);
tv0->computeAt(tv2, -2);
tv0->computeAt(tv3, -2);
// t1 allocation: 7
GpuLower gpulw(&fusion);
for (const auto expr : gpulw.kernel()->unordered_exprs()) {
if (auto alloc = dynamic_cast<kir::Allocate*>(expr)) {
auto tensor_name = alloc->buffer()->name();
if (tensor_name == 1) {
TORCH_CHECK(alloc->shape().size() == 1);
auto size = dynamic_cast<Int*>(alloc->shape().at(0));
TORCH_CHECK(
size != nullptr && size->isConst() && size->value().value() == 7);
}
}
}
int numel_x = 9;
int numel_y = 11;
auto options = at::TensorOptions().dtype(at::kFloat).device(at::kCUDA, 0);
at::Tensor t0 = at::randn({numel_x, numel_y}, options);
std::vector<IValue> inputs = {t0};
FusionExecutor fe;
fe.compileFusion(&fusion, inputs);
auto outputs = fe.runFusion(inputs);
auto t1 = t0 + 1;
auto t2 = shift(t1, {0, 1});
auto t3 = shift(t1, {0, -2});
testValidate(&fusion, outputs, inputs, {t2, t3}, __LINE__, __FILE__);
}
TEST_F(NVFuserTest, FusionShiftSplit2_CUDA) {
Fusion fusion;
FusionGuard fg(&fusion);
auto tv0 = makeSymbolicTensor(2);
fusion.addInput(tv0);
auto tv1 = add(tv0, IrBuilder::create<Double>(1));
auto tv2 = add(tv1, IrBuilder::create<Double>(1));
auto tv3 = shift(tv2, {0, -1});
auto tv4 = shift(tv2, {0, 1});
auto tv5 = add(tv3, tv4);
fusion.addOutput(tv5);
auto tv6 = add(tv0, IrBuilder::create<Double>(1));
auto tv7 = shift(tv6, {0, 0});
auto tv8 = add(tv7, IrBuilder::create<Double>(1));
fusion.addOutput(tv8);
int split_factor = 4;
tv5->split(-1, split_factor);
tv8->split(-1, split_factor);
tv0->computeAt(tv5, -2);
tv0->computeAt(tv8, -2);
// t1 and t2 allocation: 6
// t4 allocation: 4
GpuLower gpulw(&fusion);
for (const auto expr : gpulw.kernel()->unordered_exprs()) {
if (auto alloc = dynamic_cast<kir::Allocate*>(expr)) {
auto tensor_name = alloc->buffer()->name();
if (tensor_name == 1 || tensor_name == 2) {
TORCH_CHECK(alloc->shape().size() == 1);
auto size = dynamic_cast<Int*>(alloc->shape().at(0));
TORCH_CHECK(
size != nullptr && size->isConst() && size->value().value() == 6);
} else if (tensor_name == 4) {
TORCH_CHECK(alloc->shape().size() == 1);
auto size = dynamic_cast<Int*>(alloc->shape().at(0));
TORCH_CHECK(size != nullptr && size->isConst());
int size_value = *size->value();
TORCH_CHECK(size_value == split_factor);
}
}
}
int numel_x = 9;
int numel_y = 11;
auto options = at::TensorOptions().dtype(at::kFloat).device(at::kCUDA, 0);
at::Tensor t0 = at::randn({numel_x, numel_y}, options);
std::vector<IValue> inputs = {t0};
FusionExecutor fe;
fe.compileFusion(&fusion, inputs);
auto outputs = fe.runFusion(inputs);
auto t1 = t0 + 2;
auto t3 = shift(t1, {0, -1});
auto t4 = shift(t1, {0, 1});
auto t5 = t3 + t4;
auto t6 = t0 + 1;
auto t7 = t6;
auto t8 = t7 + 1;
testValidate(&fusion, outputs, inputs, {t5, t8}, __LINE__, __FILE__);
}
TEST_F(NVFuserTest, FusionShiftDoubleSplit_CUDA) {
Fusion fusion;
FusionGuard fg(&fusion);
auto tv0 = makeSymbolicTensor(2);
fusion.addInput(tv0);
auto tv1 = add(tv0, IrBuilder::create<Double>(1));
auto tv2 = add(tv1, IrBuilder::create<Double>(2));
auto tv3 = shift(tv2, {0, 1});
fusion.addOutput(tv3);
int split_factor1 = 8;
int split_factor2 = 4;
tv3->split(-1, split_factor1);
tv0->computeAt(tv3, -2);
tv1->split(-1, split_factor2);
// t1: [i1, i2/8, 8/4, 4]
// t2: [i1, i2/8, 8]
// t3: [i1, i2/8, 8]
// t1 and t2 allocation: (split_factor1 + 1) = 9
GpuLower gpulw(&fusion);
for (const auto expr : gpulw.kernel()->unordered_exprs()) {
if (auto alloc = dynamic_cast<kir::Allocate*>(expr)) {
auto tensor_name = alloc->buffer()->name();
if (tensor_name == 1 || tensor_name == 2) {
TORCH_CHECK(alloc->shape().size() == 1);
auto size = dynamic_cast<Int*>(alloc->shape().at(0));
TORCH_CHECK(
size != nullptr && size->isConst() && size->value().value() == 9);
}
}
}
int numel_x = 99;
int numel_y = 101;
auto options = at::TensorOptions().dtype(at::kFloat).device(at::kCUDA, 0);
at::Tensor t0 = at::randn({numel_x, numel_y}, options);
std::vector<IValue> inputs = {t0};
FusionExecutor fe;
fe.compileFusion(&fusion, inputs);
auto outputs = fe.runFusion(inputs);
auto t1 = t0 + 3;
auto ref = shift(t1, {0, 1});
testValidate(&fusion, outputs, inputs, {ref}, __LINE__, __FILE__);
}
TEST_F(NVFuserTest, FusionShift3ptStencil_CUDA) {
Fusion fusion;
FusionGuard fg(&fusion);
// 3-pt stencil
auto tv0 = makeSymbolicTensor(1);
fusion.addInput(tv0);
std::vector<std::vector<int>> offsets = {{-1}, {1}};
std::vector<TensorView*> tvs;
for (const auto& offset : offsets) {
tvs.push_back(shift(tv0, offset));
}
auto tv_out = tv0;
for (auto tv : tvs) {
tv_out = add(tv_out, tv);
}
tv_out = div(tv_out, IrBuilder::create<Double>(tvs.size() + 1));
fusion.addOutput(tv_out);
int split_factor = 4;
tv_out->split(0, split_factor);
// This seems fine but not verified yet
// tv_out->axis(-1)->parallelize(ParallelType::Unswitch);
auto cache = tv0->cache_after();
tv0->computeAt(tv_out, 1);
// Inline completely except for the cache
for (auto tv : tvs) {
tv->computeAt(tv_out, -1);
}
// cache allocation: (split_factor + 2)
GpuLower gpulw(&fusion);
for (const auto expr : gpulw.kernel()->unordered_exprs()) {
if (auto alloc = dynamic_cast<kir::Allocate*>(expr)) {
auto tensor_name = alloc->buffer()->name();
if (tensor_name == cache->name()) {
TORCH_CHECK(alloc->shape().size() == 1);
auto size = dynamic_cast<Int*>(alloc->shape().at(0));
TORCH_CHECK(
size != nullptr && size->isConst() &&
size->value().value() == split_factor + 2);
}
}
}
cache->doubleBuffer();
int numel_x = 99;
auto options = at::TensorOptions().dtype(at::kFloat).device(at::kCUDA, 0);
at::Tensor t0 = at::randn({numel_x}, options);
std::vector<IValue> inputs = {t0};
FusionExecutor fe;
fe.compileFusion(&fusion, inputs);
auto outputs = fe.runFusion(inputs);
auto ref = (t0 + shift(t0, {-1}) + shift(t0, {1})) / 3;
testValidate(&fusion, outputs, inputs, {ref}, __LINE__, __FILE__);
}
TEST_F(NVFuserTest, FusionShift5ptStencil_CUDA) {
Fusion fusion;
FusionGuard fg(&fusion);
// 5-pt stencil
auto tv0 = makeSymbolicTensor(2);
fusion.addInput(tv0);
std::vector<std::vector<int>> offsets = {{-1, 0}, {1, 0}, {0, -1}, {0, 1}};
std::vector<TensorView*> tvs;
for (const auto& offset : offsets) {
tvs.push_back(shift(tv0, offset));
}
auto tv_out = tv0;
for (auto tv : tvs) {
tv_out = add(tv_out, tv);
}
tv_out = div(tv_out, IrBuilder::create<Double>(tvs.size() + 1));
fusion.addOutput(tv_out);
std::vector<int> split_factor({4, 8});
tv_out->split(-1, split_factor[1]);
tv_out->split(0, split_factor[0]);
tv_out->reorder({{1, 2}, {2, 1}});
auto cache = tv0->cache_after();
tv0->computeAt(tv_out, 2);
// Inline completely except for the cache
for (auto tv : tvs) {
tv->computeAt(tv_out, -1);
}
// cache allocation: (split_factor + 2) * (split_factor + 2)
GpuLower gpulw(&fusion);
for (const auto expr : gpulw.kernel()->unordered_exprs()) {
if (auto alloc = dynamic_cast<kir::Allocate*>(expr)) {
auto tensor_name = alloc->buffer()->name();
if (tensor_name == cache->name()) {
TORCH_CHECK(alloc->shape().size() == 2);
for (int i = 0; i < 2; ++i) {
auto size = dynamic_cast<Int*>(alloc->shape().at(i));
TORCH_CHECK(
size != nullptr && size->isConst() &&
size->value().value() == split_factor[i] + 2);
}
}
}
}
cache->doubleBuffer();
int numel_x = 99;
int numel_y = 101;
auto options = at::TensorOptions().dtype(at::kFloat).device(at::kCUDA, 0);
at::Tensor t0 = at::randn({numel_x, numel_y}, options);
std::vector<IValue> inputs = {t0};
FusionExecutor fe;
fe.compileFusion(&fusion, inputs);
auto outputs = fe.runFusion(inputs);
auto ref = t0;
for (const auto& offset : offsets) {
ref = ref + shift(t0, offset);
}
ref = ref / int(offsets.size() + 1);
testValidate(&fusion, outputs, inputs, {ref}, __LINE__, __FILE__);
}
TEST_F(NVFuserTest, FusionShift9ptStencil_CUDA) {
Fusion fusion;
FusionGuard fg(&fusion);
// 9-pt stencil
std::vector<std::vector<int>> offsets;
for (int i = -1; i < 2; ++i) {
for (int j = -1; j < 2; ++j) {
if (i == 0 && j == 0) {
continue;
}
offsets.push_back({i, j});
}
}
auto tv0 = makeSymbolicTensor(2);
fusion.addInput(tv0);
std::vector<TensorView*> tvs;
for (const auto& offset : offsets) {
tvs.push_back(shift(tv0, offset));
}
auto tv_out = tv0;
for (auto tv : tvs) {
tv_out = add(tv_out, tv);
}
tv_out = div(tv_out, IrBuilder::create<Double>(tvs.size() + 1));
fusion.addOutput(tv_out);
std::vector<int> split_factor({4, 8});
tv_out->split(-1, split_factor[1]);
tv_out->split(0, split_factor[0]);
tv_out->reorder({{1, 2}, {2, 1}});
auto cache = tv0->cache_after();
tv0->computeAt(tv_out, 2);
// Inline completely except for the cache
for (auto tv : tvs) {
tv->computeAt(tv_out, -1);
}
// This seems fine but not yet verified
// tv_out->axis(-1)->parallelize(ParallelType::Unswitch);
// cache allocation: (split_factor + 2) * (split_factor + 2)
GpuLower gpulw(&fusion);
for (const auto expr : gpulw.kernel()->unordered_exprs()) {
if (auto alloc = dynamic_cast<kir::Allocate*>(expr)) {
auto tensor_name = alloc->buffer()->name();
if (tensor_name == cache->name()) {
TORCH_CHECK(alloc->shape().size() == 2);
for (int i = 0; i < 2; ++i) {
auto size = dynamic_cast<Int*>(alloc->shape().at(i));
TORCH_CHECK(
size != nullptr && size->isConst() &&
size->value().value() == split_factor[i] + 2);
}
}
}
}
cache->doubleBuffer();
int numel_x = 99;
int numel_y = 101;
auto options = at::TensorOptions().dtype(at::kFloat).device(at::kCUDA, 0);
at::Tensor t0 = at::randn({numel_x, numel_y}, options);
std::vector<IValue> inputs = {t0};
FusionExecutor fe;
fe.compileFusion(&fusion, inputs);
auto outputs = fe.runFusion(inputs);
auto ref = t0;
for (const auto& offset : offsets) {
ref = ref + shift(t0, offset);
}
ref = ref / int(offsets.size() + 1);
testValidate(&fusion, outputs, inputs, {ref}, __LINE__, __FILE__);
}
TEST_F(NVFuserTest, FusionShiftSmemBlocking_CUDA) {
Fusion fusion;
FusionGuard fg(&fusion);
auto tv0 = makeSymbolicTensor(2);
fusion.addInput(tv0);
auto tv1 = add(tv0, IrBuilder::create<Double>(1));
auto tv2 = shift(tv1, {0, 1});
fusion.addOutput(tv2);
int smem_block_factor = 32;
tv2->split(-1, smem_block_factor);
tv0->computeAt(tv2, -2);
tv1->axis(-1)->parallelize(ParallelType::TIDx);
tv2->axis(-1)->parallelize(ParallelType::TIDx);
tv1->setMemoryType(MemoryType::Shared);
// tv1 allocation: (split_factor + 1)
GpuLower gpulw(&fusion);
for (const auto expr : gpulw.kernel()->unordered_exprs()) {
if (auto alloc = dynamic_cast<kir::Allocate*>(expr)) {
auto tensor_name = alloc->buffer()->name();
if (tensor_name == tv1->name()) {
TORCH_CHECK(alloc->shape().size() == 1);
for (int i = 0; i < 1; ++i) {
auto size = dynamic_cast<Int*>(alloc->shape().at(i));
TORCH_CHECK(
size != nullptr && size->isConst() &&
size->value().value() == smem_block_factor + 1);
}
}
}
}
int numel_x = 100;
int numel_y = 101;
auto options = at::TensorOptions().dtype(at::kFloat).device(at::kCUDA, 0);
at::Tensor t0 = at::randn({numel_x, numel_y}, options);
std::vector<IValue> inputs = {t0};
FusionExecutor fe;
fe.compileFusion(&fusion, inputs);
auto outputs = fe.runFusion(inputs);
auto t1 = t0 + 1;
auto t2 = shift(t1, {0, 1});
auto ref = t2;
testValidate(&fusion, outputs, inputs, {ref}, __LINE__, __FILE__);
}
TEST_F(NVFuserTest, FusionShift3ptStencilParallel_CUDA) {
Fusion fusion;
FusionGuard fg(&fusion);
// 3-pt stencil
auto tv0 = makeSymbolicTensor(1);
fusion.addInput(tv0);
std::vector<TensorView*> tvs;
tvs.push_back(shift(tv0, {-1}));
tvs.push_back(shift(tv0, {1}));
auto tv_out = tv0;
for (auto tv : tvs) {
tv_out = add(tv_out, tv);
}
tv_out = div(tv_out, IrBuilder::create<Double>(tvs.size() + 1));
fusion.addOutput(tv_out);
int smem_block_factor = 32;
tv_out->split(0, smem_block_factor);
// tv_out->axis(-1)->parallelize(ParallelType::Unswitch);
auto tv0_cache = tv0->cache_after();
tv0->computeAt(tv_out, 1);
for (auto tv : tvs) {
tv->computeAt(tv_out, -1);
}
tv0_cache->setMemoryType(MemoryType::Shared);
tv_out->axis(-1)->parallelize(ParallelType::TIDx);
tv0_cache->axis(-1)->parallelize(ParallelType::TIDx);
tv0_cache->doubleBuffer();
int numel_x = 99;
auto options = at::TensorOptions().dtype(at::kFloat).device(at::kCUDA, 0);
at::Tensor t0 = at::randn({numel_x}, options);
std::vector<IValue> inputs = {t0};
FusionExecutor fe;
fe.compileFusion(&fusion, inputs);
auto outputs = fe.runFusion(inputs);
auto ref = (t0 + shift(t0, {-1}) + shift(t0, {1})) / 3;
testValidate(&fusion, outputs, inputs, {ref}, __LINE__, __FILE__);
}
TEST_F(NVFuserTest, FusionShift5ptStencilParallel_CUDA) {
Fusion fusion;
FusionGuard fg(&fusion);
// 5-pt stencil
auto tv0 = makeSymbolicTensor(2);
fusion.addInput(tv0);
std::vector<std::vector<int>> offsets = {{-1, 0}, {1, 0}, {0, -1}, {0, 1}};
std::vector<TensorView*> tvs;
for (const auto& offset : offsets) {
tvs.push_back(shift(tv0, offset));
}
auto tv_out = tv0;
for (auto tv : tvs) {
tv_out = add(tv_out, tv);
}
tv_out = div(tv_out, IrBuilder::create<Double>(tvs.size() + 1));
fusion.addOutput(tv_out);
int smem_block_factor = 32;
tv_out->split(-1, smem_block_factor);
tv_out->split(0, smem_block_factor);
tv_out->reorder({{1, 2}, {2, 1}});
auto tv0_cache = tv0->cache_after();
tv0->computeAt(tv_out, 2);
for (auto tv : tvs) {
tv->computeAt(tv_out, -1);
}
tv_out->axis(-1)->parallelize(ParallelType::TIDx);
tv_out->axis(-2)->parallelize(ParallelType::TIDy);
tv_out->axis(-3)->parallelize(ParallelType::BIDx);
tv_out->axis(-4)->parallelize(ParallelType::BIDy);
tv0_cache->setMemoryType(MemoryType::Shared);
tv0_cache->axis(-1)->parallelize(ParallelType::TIDx);
tv0_cache->axis(-2)->parallelize(ParallelType::TIDy);
int numel_x = 99;
int numel_y = 101;
auto options = at::TensorOptions().dtype(at::kFloat).device(at::kCUDA, 0);
at::Tensor t0 = at::randn({numel_x, numel_y}, options);
std::vector<IValue> inputs = {t0};
FusionExecutor fe;
fe.compileFusion(&fusion, inputs);
auto outputs = fe.runFusion(inputs);
auto ref = t0;