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Copy pathlooprestoration_sse.asm
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looprestoration_sse.asm
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; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; Copyright © 2018, VideoLabs
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice, this
; list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
%include "config.asm"
%include "ext/x86/x86inc.asm"
SECTION_RODATA 16
wiener_init: db 6, 7, 6, 7, 6, 7, 6, 7, 0, 0, 0, 0, 2, 4, 2, 4
wiener_shufA: db 1, 7, 2, 8, 3, 9, 4, 10, 5, 11, 6, 12, 7, 13, 8, 14
wiener_shufB: db 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10
wiener_shufC: db 6, 5, 7, 6, 8, 7, 9, 8, 10, 9, 11, 10, 12, 11, 13, 12
wiener_shufD: db 4, -1, 5, -1, 6, -1, 7, -1, 8, -1, 9, -1, 10, -1, 11, -1
wiener_l_shuf: db 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11
sgr_lshuf3: db 0, 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
sgr_lshuf5: db 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12
pb_0to15: db 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
pb_right_ext_mask: times 24 db 0xff
times 8 db 0
pb_1: times 16 db 1
pb_3: times 16 db 3
pw_256: times 8 dw 256
pw_2056: times 8 dw 2056
pw_m16380: times 8 dw -16380
pd_4096: times 4 dd 4096
pd_34816: times 4 dd 34816
pd_0xffff: times 4 dd 0xffff
pd_0xf00800a4: times 4 dd 0xf00800a4
pd_0xf00801c7: times 4 dd 0xf00801c7
cextern sgr_x_by_x
SECTION .text
%macro movif64 2 ; dst, src
%if ARCH_X86_64
mov %1, %2
%endif
%endmacro
%macro movif32 2 ; dst, src
%if ARCH_X86_32
mov %1, %2
%endif
%endmacro
%if ARCH_X86_32
%define PIC_base_offset $$
%macro SETUP_PIC 1-3 1,0 ; PIC_reg, save_PIC_reg, restore_PIC_reg
%assign pic_reg_stk_off 4
%xdefine PIC_reg %1
%if %2 == 1
mov [esp], %1
%endif
LEA PIC_reg, PIC_base_offset
%if %3 == 1
XCHG_PIC_REG
%endif
%endmacro
%macro XCHG_PIC_REG 0
mov [esp+pic_reg_stk_off], PIC_reg
%assign pic_reg_stk_off (pic_reg_stk_off+4) % 8
mov PIC_reg, [esp+pic_reg_stk_off]
%endmacro
%define PIC_sym(sym) (PIC_reg+(sym)-PIC_base_offset)
%else
%macro XCHG_PIC_REG 0
%endmacro
%define PIC_sym(sym) (sym)
%endif
%macro WIENER 0
%if ARCH_X86_64
DECLARE_REG_TMP 9, 7, 10, 11, 12, 13, 14 ; ring buffer pointers
cglobal wiener_filter7_8bpc, 4, 15, 16, -384*12-16, dst, stride, left, lpf, \
w, h, edge, flt, x
%define tmpstrideq strideq
%define base 0
mov fltq, r6mp
mov wd, wm
movifnidn hd, hm
mov edged, r7m
movq m14, [fltq]
add lpfq, wq
movq m7, [fltq+16]
add dstq, wq
lea t1, [rsp+wq*2+16]
mova m15, [pw_2056]
neg wq
%if cpuflag(ssse3)
pshufb m14, [wiener_init]
mova m8, [wiener_shufA]
pshufd m12, m14, q2222 ; x0 x0
mova m9, [wiener_shufB]
pshufd m13, m14, q3333 ; x1 x2
mova m10, [wiener_shufC]
punpcklqdq m14, m14 ; x3
mova m11, [wiener_shufD]
%else
mova m10, [pw_m16380]
punpcklwd m14, m14
pshufd m11, m14, q0000 ; x0
pshufd m12, m14, q1111 ; x1
pshufd m13, m14, q2222 ; x2
pshufd m14, m14, q3333 ; x3
%endif
%else
DECLARE_REG_TMP 4, 0, _, 5
%if cpuflag(ssse3)
%define m10 [base+wiener_shufC]
%define m11 [base+wiener_shufD]
%define stk_off 96
%else
%define m10 [base+pw_m16380]
%define m11 [stk+96]
%define stk_off 112
%endif
cglobal wiener_filter7_8bpc, 0, 7, 8, -384*12-stk_off, _, x, left, lpf, tmpstride
%define base r6-pb_right_ext_mask-21
%define stk esp
%define dstq leftq
%define edgeb byte edged
%define edged [stk+ 8]
%define dstmp [stk+12]
%define hd dword [stk+16]
%define wq [stk+20]
%define strideq [stk+24]
%define leftmp [stk+28]
%define t2 [stk+32]
%define t4 [stk+36]
%define t5 [stk+40]
%define t6 [stk+44]
%define m8 [base+wiener_shufA]
%define m9 [base+wiener_shufB]
%define m12 [stk+48]
%define m13 [stk+64]
%define m14 [stk+80]
%define m15 [base+pw_2056]
mov r1, r6m ; flt
mov r0, r0m ; dst
mov r4, r4m ; w
mov lpfq, lpfm
mov r2, r7m ; edge
mov r5, r5m ; h
movq m3, [r1+ 0]
movq m7, [r1+16]
add r0, r4
mov r1, r1m ; stride
add lpfq, r4
mov edged, r2
mov r2, r2m ; left
mov dstmp, r0
lea t1, [rsp+r4*2+stk_off]
mov hd, r5
neg r4
LEA r6, pb_right_ext_mask+21
mov wq, r4
mov strideq, r1
mov leftmp, r2
mov r4, r1
%if cpuflag(ssse3)
pshufb m3, [base+wiener_init]
pshufd m1, m3, q2222
pshufd m2, m3, q3333
punpcklqdq m3, m3
%else
punpcklwd m3, m3
pshufd m0, m3, q0000
pshufd m1, m3, q1111
pshufd m2, m3, q2222
pshufd m3, m3, q3333
mova m11, m0
%endif
mova m12, m1
mova m13, m2
mova m14, m3
%endif
psllw m7, 5
pshufd m6, m7, q0000 ; y0 y1
pshufd m7, m7, q1111 ; y2 y3
test edgeb, 4 ; LR_HAVE_TOP
jz .no_top
call .h_top
add lpfq, strideq
mov t6, t1
mov t5, t1
add t1, 384*2
call .h_top
lea t3, [lpfq+tmpstrideq*4]
mov lpfq, dstmp
add t3, tmpstrideq
mov [rsp], t3 ; below
mov t4, t1
add t1, 384*2
call .h
mov t3, t1
mov t2, t1
dec hd
jz .v1
add lpfq, strideq
add t1, 384*2
call .h
mov t2, t1
dec hd
jz .v2
add lpfq, strideq
add t1, 384*2
call .h
dec hd
jz .v3
.main:
lea t0, [t1+384*2]
.main_loop:
call .hv
dec hd
jnz .main_loop
test edgeb, 8 ; LR_HAVE_BOTTOM
jz .v3
mov lpfq, [rsp]
call .hv_bottom
add lpfq, strideq
call .hv_bottom
.v1:
call mangle(private_prefix %+ _wiener_filter7_8bpc_ssse3).v
RET
.no_top:
lea t3, [lpfq+tmpstrideq*4]
mov lpfq, dstmp
lea t3, [t3+tmpstrideq*2]
mov [rsp], t3
call .h
mov t6, t1
mov t5, t1
mov t4, t1
mov t3, t1
mov t2, t1
dec hd
jz .v1
add lpfq, strideq
add t1, 384*2
call .h
mov t2, t1
dec hd
jz .v2
add lpfq, strideq
add t1, 384*2
call .h
dec hd
jz .v3
lea t0, [t1+384*2]
call .hv
dec hd
jz .v3
add t0, 384*8
call .hv
dec hd
jnz .main
.v3:
call mangle(private_prefix %+ _wiener_filter7_8bpc_ssse3).v
.v2:
call mangle(private_prefix %+ _wiener_filter7_8bpc_ssse3).v
jmp .v1
.extend_right:
movd m2, [lpfq-4]
%if ARCH_X86_64
push r0
lea r0, [pb_right_ext_mask+21]
movu m0, [r0+xq+0]
movu m1, [r0+xq+8]
pop r0
%else
movu m0, [r6+xq+0]
movu m1, [r6+xq+8]
%endif
%if cpuflag(ssse3)
pshufb m2, [base+pb_3]
%else
punpcklbw m2, m2
pshuflw m2, m2, q3333
punpcklqdq m2, m2
%endif
pand m4, m0
pand m5, m1
pandn m0, m2
pandn m1, m2
por m4, m0
por m5, m1
ret
.h:
%define stk esp+4 ; offset due to call
mov xq, wq
test edgeb, 1 ; LR_HAVE_LEFT
jz .h_extend_left
movifnidn leftq, leftmp
mova m4, [lpfq+xq]
movd m5, [leftq]
add leftq, 4
pslldq m4, 4
por m4, m5
movifnidn leftmp, leftq
jmp .h_main
.h_extend_left:
%if cpuflag(ssse3)
mova m4, [lpfq+xq]
pshufb m4, [base+wiener_l_shuf]
%else
mova m5, [lpfq+xq]
pshufd m4, m5, q2103
punpcklbw m5, m5
punpcklwd m5, m5
movss m4, m5
%endif
jmp .h_main
.h_top:
mov xq, wq
test edgeb, 1 ; LR_HAVE_LEFT
jz .h_extend_left
.h_loop:
movu m4, [lpfq+xq-4]
.h_main:
movu m5, [lpfq+xq+4]
test edgeb, 2 ; LR_HAVE_RIGHT
jnz .h_have_right
cmp xd, -18
jl .h_have_right
call .extend_right
.h_have_right:
%macro %%h7 0
%if cpuflag(ssse3)
pshufb m0, m4, m8
pmaddubsw m0, m12
pshufb m1, m5, m8
pmaddubsw m1, m12
pshufb m2, m4, m9
pmaddubsw m2, m13
pshufb m3, m5, m9
pmaddubsw m3, m13
paddw m0, m2
pshufb m2, m4, m10
pmaddubsw m2, m13
paddw m1, m3
pshufb m3, m5, m10
pmaddubsw m3, m13
pshufb m4, m11
paddw m0, m2
pmullw m2, m14, m4
pshufb m5, m11
paddw m1, m3
pmullw m3, m14, m5
psllw m4, 7
psllw m5, 7
paddw m0, m2
mova m2, [base+pw_m16380]
paddw m1, m3
paddw m4, m2
paddw m5, m2
paddsw m0, m4
paddsw m1, m5
%else
psrldq m0, m4, 1
pslldq m1, m4, 1
pxor m3, m3
punpcklbw m0, m3
punpckhbw m1, m3
paddw m0, m1
pmullw m0, m11
psrldq m1, m4, 2
pslldq m2, m4, 2
punpcklbw m1, m3
punpckhbw m2, m3
paddw m1, m2
pmullw m1, m12
paddw m0, m1
pshufd m2, m4, q0321
punpcklbw m2, m3
pmullw m1, m14, m2
paddw m0, m1
psrldq m1, m4, 3
pslldq m4, 3
punpcklbw m1, m3
punpckhbw m4, m3
paddw m1, m4
pmullw m1, m13
paddw m0, m1
psllw m2, 7
paddw m2, m10
paddsw m0, m2
psrldq m1, m5, 1
pslldq m2, m5, 1
punpcklbw m1, m3
punpckhbw m2, m3
paddw m1, m2
pmullw m1, m11
psrldq m2, m5, 2
pslldq m4, m5, 2
punpcklbw m2, m3
punpckhbw m4, m3
paddw m2, m4
pmullw m2, m12
paddw m1, m2
pshufd m4, m5, q0321
punpcklbw m4, m3
pmullw m2, m14, m4
paddw m1, m2
psrldq m2, m5, 3
pslldq m5, 3
punpcklbw m2, m3
punpckhbw m5, m3
paddw m2, m5
pmullw m2, m13
paddw m1, m2
psllw m4, 7
paddw m4, m10
paddsw m1, m4
%endif
%endmacro
%%h7
psraw m0, 3
psraw m1, 3
paddw m0, m15
paddw m1, m15
mova [t1+xq*2+ 0], m0
mova [t1+xq*2+16], m1
add xq, 16
jl .h_loop
ret
ALIGN function_align
.hv:
add lpfq, strideq
mov xq, wq
test edgeb, 1 ; LR_HAVE_LEFT
jz .hv_extend_left
movifnidn leftq, leftmp
mova m4, [lpfq+xq]
movd m5, [leftq]
add leftq, 4
pslldq m4, 4
por m4, m5
movifnidn leftmp, leftq
jmp .hv_main
.hv_extend_left:
%if cpuflag(ssse3)
mova m4, [lpfq+xq]
pshufb m4, [base+wiener_l_shuf]
%else
mova m5, [lpfq+xq]
pshufd m4, m5, q2103
punpcklbw m5, m5
punpcklwd m5, m5
movss m4, m5
%endif
jmp .hv_main
.hv_bottom:
mov xq, wq
test edgeb, 1 ; LR_HAVE_LEFT
jz .hv_extend_left
.hv_loop:
movu m4, [lpfq+xq-4]
.hv_main:
movu m5, [lpfq+xq+4]
test edgeb, 2 ; LR_HAVE_RIGHT
jnz .hv_have_right
cmp xd, -18
jl .hv_have_right
call .extend_right
.hv_have_right:
%%h7
%if ARCH_X86_64
mova m2, [t4+xq*2]
paddw m2, [t2+xq*2]
%else
mov r2, t4
mova m2, [r2+xq*2]
mov r2, t2
paddw m2, [r2+xq*2]
mov r2, t5
%endif
mova m3, [t3+xq*2]
%if ARCH_X86_64
mova m5, [t5+xq*2]
%else
mova m5, [r2+xq*2]
mov r2, t6
%endif
paddw m5, [t1+xq*2]
psraw m0, 3
psraw m1, 3
paddw m0, m15
paddw m1, m15
%if ARCH_X86_64
paddw m4, m0, [t6+xq*2]
%else
paddw m4, m0, [r2+xq*2]
mov r2, t4
%endif
mova [t0+xq*2], m0
punpcklwd m0, m2, m3
pmaddwd m0, m7
punpckhwd m2, m3
pmaddwd m2, m7
punpcklwd m3, m4, m5
pmaddwd m3, m6
punpckhwd m4, m5
pmaddwd m4, m6
paddd m0, m3
mova m3, [t3+xq*2+16]
paddd m4, m2
%if ARCH_X86_64
mova m2, [t4+xq*2+16]
paddw m2, [t2+xq*2+16]
mova m5, [t5+xq*2+16]
%else
mova m2, [r2+xq*2+16]
mov r2, t2
paddw m2, [r2+xq*2+16]
mov r2, t5
mova m5, [r2+xq*2+16]
mov r2, t6
%endif
paddw m5, [t1+xq*2+16]
packuswb m0, m4
%if ARCH_X86_64
paddw m4, m1, [t6+xq*2+16]
%else
paddw m4, m1, [r2+xq*2+16]
mov dstq, dstmp
%endif
mova [t0+xq*2+16], m1
punpcklwd m1, m2, m3
pmaddwd m1, m7
punpckhwd m2, m3
pmaddwd m2, m7
punpcklwd m3, m4, m5
pmaddwd m3, m6
punpckhwd m4, m5
pmaddwd m4, m6
paddd m1, m3
paddd m2, m4
packuswb m1, m2
psrlw m0, 8
psrlw m1, 8
packuswb m0, m1
mova [dstq+xq], m0
add xq, 16
jl .hv_loop
add dstq, strideq
%if ARCH_X86_64
mov t6, t5
mov t5, t4
mov t4, t3
mov t3, t2
mov t2, t1
mov t1, t0
mov t0, t6
%else
mov dstmp, dstq
mov r1, t5
mov r2, t4
mov t6, r1
mov t5, r2
mov t4, t3
mov t3, t2
mov t2, t1
mov t1, t0
mov t0, r1
%endif
ret
%if cpuflag(ssse3) ; identical in sse2 and ssse3, so share code
.v:
mov xq, wq
.v_loop:
%if ARCH_X86_64
mova m1, [t4+xq*2]
paddw m1, [t2+xq*2]
%else
mov r2, t4
mova m1, [r2+xq*2]
mov r2, t2
paddw m1, [r2+xq*2]
mov r2, t6
%endif
mova m2, [t3+xq*2]
mova m4, [t1+xq*2]
%if ARCH_X86_64
paddw m3, m4, [t6+xq*2]
paddw m4, [t5+xq*2]
%else
paddw m3, m4, [r2+xq*2]
mov r2, t5
paddw m4, [r2+xq*2]
mov r2, t4
%endif
punpcklwd m0, m1, m2
pmaddwd m0, m7
punpckhwd m1, m2
pmaddwd m1, m7
punpcklwd m2, m3, m4
pmaddwd m2, m6
punpckhwd m3, m4
pmaddwd m3, m6
paddd m0, m2
paddd m1, m3
%if ARCH_X86_64
mova m2, [t4+xq*2+16]
paddw m2, [t2+xq*2+16]
%else
mova m2, [r2+xq*2+16]
mov r2, t2
paddw m2, [r2+xq*2+16]
mov r2, t6
%endif
mova m3, [t3+xq*2+16]
mova m5, [t1+xq*2+16]
%if ARCH_X86_64
paddw m4, m5, [t6+xq*2+16]
paddw m5, [t5+xq*2+16]
%else
paddw m4, m5, [r2+xq*2+16]
mov r2, t5
paddw m5, [r2+xq*2+16]
movifnidn dstq, dstmp
%endif
packuswb m0, m1
punpcklwd m1, m2, m3
pmaddwd m1, m7
punpckhwd m2, m3
pmaddwd m2, m7
punpcklwd m3, m4, m5
pmaddwd m3, m6
punpckhwd m4, m5
pmaddwd m4, m6
paddd m1, m3
paddd m2, m4
packuswb m1, m2
psrlw m0, 8
psrlw m1, 8
packuswb m0, m1
mova [dstq+xq], m0
add xq, 16
jl .v_loop
add dstq, strideq
%if ARCH_X86_64
mov t6, t5
mov t5, t4
%else
mov dstmp, dstq
mov r1, t5
mov r2, t4
mov t6, r1
mov t5, r2
%endif
mov t4, t3
mov t3, t2
mov t2, t1
ret
%endif
%if ARCH_X86_64
cglobal wiener_filter5_8bpc, 4, 13, 16, 384*8+16, dst, stride, left, lpf, \
w, h, edge, flt, x
mov fltq, r6mp
mov wd, wm
movifnidn hd, hm
mov edged, r7m
movq m14, [fltq]
add lpfq, wq
movq m7, [fltq+16]
add dstq, wq
mova m8, [pw_m16380]
lea t1, [rsp+wq*2+16]
mova m15, [pw_2056]
neg wq
%if cpuflag(ssse3)
pshufb m14, [wiener_init]
mova m9, [wiener_shufB]
pshufd m13, m14, q3333 ; x1 x2
mova m10, [wiener_shufC]
punpcklqdq m14, m14 ; x3
mova m11, [wiener_shufD]
mova m12, [wiener_l_shuf]
%else
punpcklwd m14, m14
pshufd m11, m14, q1111 ; x1
pshufd m13, m14, q2222 ; x2
pshufd m14, m14, q3333 ; x3
%endif
%else
%if cpuflag(ssse3)
%define stk_off 80
%else
%define m11 [stk+80]
%define stk_off 96
%endif
cglobal wiener_filter5_8bpc, 0, 7, 8, -384*8-stk_off, _, x, left, lpf, tmpstride
%define stk esp
%define leftmp [stk+28]
%define m8 [base+pw_m16380]
%define m12 [base+wiener_l_shuf]
%define m14 [stk+48]
mov r1, r6m ; flt
mov r0, r0m ; dst
mov r4, r4m ; w
mov lpfq, lpfm
mov r2, r7m ; edge
mov r5, r5m ; h
movq m2, [r1+ 0]
movq m7, [r1+16]
add r0, r4
mov r1, r1m ; stride
add lpfq, r4
mov edged, r2
mov r2, r2m ; left
mov dstmp, r0
lea t1, [rsp+r4*2+stk_off]
mov hd, r5
neg r4
LEA r6, pb_right_ext_mask+21
mov wq, r4
mov strideq, r1
mov leftmp, r2
mov r4, r1
%if cpuflag(ssse3)
pshufb m2, [base+wiener_init]
pshufd m1, m2, q3333
punpcklqdq m2, m2
%else
punpcklwd m2, m2
pshufd m0, m2, q1111
pshufd m1, m2, q2222
pshufd m2, m2, q3333
mova m11, m0
%endif
mova m13, m1
mova m14, m2
%endif
psllw m7, 5
pshufd m6, m7, q0000 ; __ y1
pshufd m7, m7, q1111 ; y2 y3
test edgeb, 4 ; LR_HAVE_TOP
jz .no_top
call .h_top
add lpfq, strideq
mov t4, t1
add t1, 384*2
call .h_top
lea xq, [lpfq+tmpstrideq*4]
mov lpfq, dstmp
mov t3, t1
add t1, 384*2
add xq, tmpstrideq
mov [rsp], xq ; below
call .h
mov t2, t1
dec hd
jz .v1
add lpfq, strideq
add t1, 384*2
call .h
dec hd
jz .v2
.main:
mov t0, t4
.main_loop:
call .hv
dec hd
jnz .main_loop
test edgeb, 8 ; LR_HAVE_BOTTOM
jz .v2
mov lpfq, [rsp]
call .hv_bottom
add lpfq, strideq
call .hv_bottom
.end:
RET
.no_top:
lea t3, [lpfq+tmpstrideq*4]
mov lpfq, dstmp
lea t3, [t3+tmpstrideq*2]
mov [rsp], t3
call .h
mov t4, t1
mov t3, t1
mov t2, t1
dec hd
jz .v1
add lpfq, strideq
add t1, 384*2
call .h
dec hd
jz .v2
lea t0, [t1+384*2]
call .hv
dec hd
jz .v2
add t0, 384*6
call .hv
dec hd
jnz .main
.v2:
call mangle(private_prefix %+ _wiener_filter5_8bpc_ssse3).v
add dstq, strideq
mov t4, t3
mov t3, t2
mov t2, t1
movifnidn dstmp, dstq
.v1:
call mangle(private_prefix %+ _wiener_filter5_8bpc_ssse3).v
jmp .end
.h:
%define stk esp+4
mov xq, wq
test edgeb, 1 ; LR_HAVE_LEFT
jz .h_extend_left
movifnidn leftq, leftmp
mova m4, [lpfq+xq]
movd m5, [leftq]
add leftq, 4
pslldq m4, 4
por m4, m5
movifnidn leftmp, leftq
jmp .h_main
.h_extend_left:
%if cpuflag(ssse3)
mova m4, [lpfq+xq]
pshufb m4, m12
%else
mova m5, [lpfq+xq]
pshufd m4, m5, q2103
punpcklbw m5, m5
punpcklwd m5, m5
movss m4, m5
%endif
jmp .h_main
.h_top:
mov xq, wq
test edgeb, 1 ; LR_HAVE_LEFT
jz .h_extend_left
.h_loop:
movu m4, [lpfq+xq-4]
.h_main:
movu m5, [lpfq+xq+4]
test edgeb, 2 ; LR_HAVE_RIGHT
jnz .h_have_right
cmp xd, -17
jl .h_have_right
call mangle(private_prefix %+ _wiener_filter7_8bpc %+ SUFFIX).extend_right
.h_have_right:
%macro %%h5 0
%if cpuflag(ssse3)
pshufb m0, m4, m9
pmaddubsw m0, m13
pshufb m1, m5, m9
pmaddubsw m1, m13
pshufb m2, m4, m10
pmaddubsw m2, m13
pshufb m3, m5, m10
pmaddubsw m3, m13
pshufb m4, m11
paddw m0, m2
pmullw m2, m14, m4
pshufb m5, m11
paddw m1, m3
pmullw m3, m14, m5
psllw m4, 7
psllw m5, 7
paddw m4, m8
paddw m5, m8
paddw m0, m2
paddw m1, m3
paddsw m0, m4
paddsw m1, m5
%else
psrldq m0, m4, 2
pslldq m1, m4, 2
pxor m3, m3
punpcklbw m0, m3
punpckhbw m1, m3
paddw m0, m1
pmullw m0, m11
pshufd m2, m4, q0321
punpcklbw m2, m3
pmullw m1, m14, m2
paddw m0, m1
psrldq m1, m4, 3
pslldq m4, 3
punpcklbw m1, m3
punpckhbw m4, m3
paddw m1, m4
pmullw m1, m13
paddw m0, m1
psllw m2, 7
paddw m2, m8
paddsw m0, m2
psrldq m1, m5, 2
pslldq m4, m5, 2
punpcklbw m1, m3
punpckhbw m4, m3
paddw m1, m4
pmullw m1, m11
pshufd m4, m5, q0321
punpcklbw m4, m3
pmullw m2, m14, m4
paddw m1, m2
psrldq m2, m5, 3
pslldq m5, 3
punpcklbw m2, m3
punpckhbw m5, m3
paddw m2, m5
pmullw m2, m13
paddw m1, m2
psllw m4, 7
paddw m4, m8
paddsw m1, m4
%endif
%endmacro
%%h5
psraw m0, 3
psraw m1, 3
paddw m0, m15
paddw m1, m15
mova [t1+xq*2+ 0], m0
mova [t1+xq*2+16], m1
add xq, 16
jl .h_loop
ret
ALIGN function_align
.hv:
add lpfq, strideq
mov xq, wq
test edgeb, 1 ; LR_HAVE_LEFT
jz .hv_extend_left
movifnidn leftq, leftmp
mova m4, [lpfq+xq]
movd m5, [leftq]
add leftq, 4
pslldq m4, 4
por m4, m5
movifnidn leftmp, leftq
jmp .hv_main
.hv_extend_left:
%if cpuflag(ssse3)
mova m4, [lpfq+xq]
pshufb m4, m12
%else
mova m5, [lpfq+xq]
pshufd m4, m5, q2103
punpcklbw m5, m5
punpcklwd m5, m5
movss m4, m5
%endif
jmp .hv_main
.hv_bottom:
mov xq, wq
test edgeb, 1 ; LR_HAVE_LEFT
jz .hv_extend_left
.hv_loop:
movu m4, [lpfq+xq-4]
.hv_main:
movu m5, [lpfq+xq+4]
test edgeb, 2 ; LR_HAVE_RIGHT
jnz .hv_have_right
cmp xd, -17
jl .hv_have_right
call mangle(private_prefix %+ _wiener_filter7_8bpc %+ SUFFIX).extend_right
.hv_have_right:
%%h5
mova m2, [t3+xq*2]
paddw m2, [t1+xq*2]
psraw m0, 3
psraw m1, 3
paddw m0, m15