Force zero tail for risc-v vcompress

serge-sans-paille · serge-sans-paille · commit 78cce4ae6110 · 2024-10-29T12:51:05.000Z
Fix #1060
diff --git a/include/xsimd/arch/xsimd_rvv.hpp b/include/xsimd/arch/xsimd_rvv.hpp
@@ -1129,13 +1129,14 @@ namespace xsimd
          *************/
         namespace detail
         {
-            XSIMD_RVV_OVERLOAD(rvvcompress, (__riscv_vcompress), , vec(vec, bvec))
+            XSIMD_RVV_OVERLOAD(rvvcompress, (__riscv_vcompress_tu), , vec(vec, vec, bvec))
         }
         // compress
         template <class A, class T>
         XSIMD_INLINE batch<T, A> compress(batch<T, A> const& x, batch_bool<T, A> const& mask, requires_arch<rvv>) noexcept
         {
-            return detail::rvvcompress(x, mask);
+            auto zero = broadcast<A>(T(0), rvv {});
+            return detail::rvvcompress(zero, x, mask);
         }
 
         /***************

Original file line number	Diff line number	Diff line change
`@@ -1129,13 +1129,14 @@ namespace xsimd`
`1129`	`1129`	`*************/`
`1130`	`1130`	`namespace detail`
`1131`	`1131`	`{`
`1132`		`- XSIMD_RVV_OVERLOAD(rvvcompress, (__riscv_vcompress), , vec(vec, bvec))`
	`1132`	`+ XSIMD_RVV_OVERLOAD(rvvcompress, (__riscv_vcompress_tu), , vec(vec, vec, bvec))`
`1133`	`1133`	`}`
`1134`	`1134`	`// compress`
`1135`	`1135`	`template <class A, class T>`
`1136`	`1136`	`XSIMD_INLINE batch<T, A> compress(batch<T, A> const& x, batch_bool<T, A> const& mask, requires_arch<rvv>) noexcept`
`1137`	`1137`	`{`
`1138`		`- return detail::rvvcompress(x, mask);`
	`1138`	`+ auto zero = broadcast<A>(T(0), rvv {});`
	`1139`	`+ return detail::rvvcompress(zero, x, mask);`
`1139`	`1140`	`}`
`1140`	`1141`
`1141`	`1142`	`/***************`