stm32l4, stm32f7, stm32h7: fix qspi (unused) register addresses

Author: kk-thrane

arch/arm/src/stm32f7/hardware/stm32_qspi.h

@@ -207,7 +207,7 @@
 /* Low-Power Timeout Register */
 
 #define QSPI_LPTR_TIMEOUT_SHIFT    (0)        /* Bits 0-15: Timeout period */
-#define QSPI_LPTR_TIMEOUT_MASK     (0xFFff << QSPI_PIR_INTERVAL_SHIFT)
+#define QSPI_LPTR_TIMEOUT_MASK     (0xFFff << QSPI_LPTR_TIMEOUT_SHIFT)
 
 /****************************************************************************
  * Public Types

arch/arm/src/stm32h7/hardware/stm32_qspi.h

@@ -207,7 +207,7 @@
 /* Low-Power Timeout Register */
 
 #define QSPI_LPTR_TIMEOUT_SHIFT    (0)        /* Bits 0-15: Timeout period */
-#define QSPI_LPTR_TIMEOUT_MASK     (0xFFff << QSPI_PIR_INTERVAL_SHIFT)
+#define QSPI_LPTR_TIMEOUT_MASK     (0xFFff << QSPI_LPTR_TIMEOUT_SHIFT)
 
 /****************************************************************************
  * Public Types

arch/arm/src/stm32h7/stm32_qspi.c

@@ -549,7 +549,7 @@ static void qspi_dumpregs(struct stm32h7_qspidev_s *priv, const char *msg)
           (regval & QSPI_CCR_INSTRUCTION_MASK) >> QSPI_CCR_INSTRUCTION_SHIFT,
           (regval & QSPI_CCR_IMODE_MASK) >> QSPI_CCR_IMODE_SHIFT,
           (regval & QSPI_CCR_ADMODE_MASK) >> QSPI_CCR_ADMODE_SHIFT,
-          (regval & QSPI_CCR_ADSIZE_MASK) >> QSPI_CCR_ABSIZE_SHIFT,
+          (regval & QSPI_CCR_ADSIZE_MASK) >> QSPI_CCR_ADSIZE_SHIFT,
           (regval & QSPI_CCR_ABMODE_MASK) >> QSPI_CCR_ABMODE_SHIFT,
           (regval & QSPI_CCR_ABSIZE_MASK) >> QSPI_CCR_ABSIZE_SHIFT,
           (regval & QSPI_CCR_DCYC_MASK) >> QSPI_CCR_DCYC_SHIFT,

arch/arm/src/stm32l4/hardware/stm32l4_qspi.h

@@ -205,7 +205,7 @@
 /* Low-Power Timeout Register */
 
 #define QSPI_LPTR_TIMEOUT_SHIFT    (0)        /* Bits 0-15: Timeout period */
-#define QSPI_LPTR_TIMEOUT_MASK     (0xFFff << QSPI_PIR_INTERVAL_SHIFT)
+#define QSPI_LPTR_TIMEOUT_MASK     (0xFFff << QSPI_LPTR_TIMEOUT_SHIFT)
 
 /****************************************************************************
  * Public Types