riscv/nuttsbi: add MTVAL argument

The MTVAL and the other two provides a complete exception story. Signed-off-by: Yanfeng Liu <[email protected]>
yf13 · Jun 23, 2024 · bc8a4e4 · bc8a4e4
1 parent ed78646
commit bc8a4e4
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Showing 2 changed files with 5 additions and 3 deletions.
diff --git a/arch/risc-v/src/nuttsbi/sbi_mexception.c b/arch/risc-v/src/nuttsbi/sbi_mexception.c
@@ -30,8 +30,9 @@
  * Public Functions
  ****************************************************************************/
 
-void sbi_mexception(uintptr_t mcause, uintptr_t *mepc)
+void sbi_mexception(uintreg_t mcause, uintreg_t *mepc, uintreg_t tval)
 {
-  (void) mcause;
-  (void) mepc;
+  UNUSED(mcause);
+  UNUSED(mepc);
+  UNUSED(tval);
 }
diff --git a/arch/risc-v/src/nuttsbi/sbi_mtrap.S b/arch/risc-v/src/nuttsbi/sbi_mtrap.S
@@ -127,6 +127,7 @@ machine_trap:
 
   csrr        a0, CSR_MCAUSE     /* Interrupt cause [arg0] */
   csrr        a1, CSR_MEPC       /* Interrupt PC (instruction) [arg1] */
+  csrr        a2, CSR_MTVAL      /* The MTVAL value [arg2] */
   jal         x1, sbi_mexception
   j           __start