diff --git a/boards/README.md b/boards/README.md index 07c783f4..aedffd81 100644 --- a/boards/README.md +++ b/boards/README.md @@ -60,6 +60,10 @@ * karnix_ecp5_yosys * orangecrab_ecp5_yosys +## Orange Pi + +* Orange Pi MSOC + ## Efinix (partial support) ## Others diff --git a/boards/orangepi_msoc/board_specific.cst b/boards/orangepi_msoc/board_specific.cst new file mode 100644 index 00000000..1e665057 --- /dev/null +++ b/boards/orangepi_msoc/board_specific.cst @@ -0,0 +1,97 @@ +// The pin assignments + +// CLK +IO_LOC "CLK" V18; + +// LED +IO_LOC "LED[0]" N13; // 1 +IO_LOC "LED[1]" P14; // 2 +IO_LOC "LED[2]" R14; // 3 +IO_LOC "LED[3]" N14; // 4 +IO_LOC "LED[4]" P15; // 5 +IO_LOC "LED[5]" P16; // 6 +IO_LOC "LED[6]" R16; // 7 +IO_LOC "LED[7]" P17; // 8 +IO_LOC "LED[8]" T18; // 9 +IO_LOC "LED[9]" R18; // 10 +IO_LOC "LED[10]" R17; // 11 +IO_LOC "LED[11]" W22; // 12 +IO_LOC "LED[12]" Y22; // 13 +IO_LOC "LED[13]" AA21; // 14 +IO_LOC "LED[14]" AB22; // 15 +IO_LOC "LED[15]" AB21; // 16 + +// UART +IO_LOC "UART_RX" Y19; +IO_LOC "UART_TX" U20; + +// SWITCH +IO_LOC "SW[0]" U18; // 1.1 +IO_LOC "SW[1]" U17; // 1.2 +IO_LOC "SW[2]" W17; // 1.3 +IO_LOC "SW[3]" V17; // 1.4 +IO_LOC "SW[4]" AA19; // 1.5 +IO_LOC "SW[5]" AA18; // 1.6 +IO_LOC "SW[6]" AB18; // 1.7 +IO_LOC "SW[7]" AB20; // 1.8 +IO_LOC "SW[8]" V10; // 2.1 +IO_LOC "SW[9]" AB12; // 2.2 +IO_LOC "SW[10]" W10; // 2.3 +IO_LOC "SW[11]" AA11; // 2.4 +IO_LOC "SW[12]" AA10; // 2.5 +IO_LOC "SW[13]" AB11; // 2.6 +IO_LOC "SW[14]" AA9; // 2.7 +IO_LOC "SW[15]" AB10; // 2.8 + +// KEY +IO_LOC "KEY[0]" V20; // 1 +IO_LOC "KEY[1]" W19; // 2 +IO_LOC "KEY[2]" W20; // 3 +IO_LOC "KEY[3]" W21; // 4 + +// 7SEG +IO_LOC "HGFEDCBA[0]" M21; // A +IO_LOC "HGFEDCBA[1]" L21; // B +IO_LOC "HGFEDCBA[2]" M17; // C +IO_LOC "HGFEDCBA[3]" J22; // D +IO_LOC "HGFEDCBA[4]" H22; // E +IO_LOC "HGFEDCBA[5]" K21; // F +IO_LOC "HGFEDCBA[6]" K22; // G +IO_LOC "HGFEDCBA[7]" J20; // Dot +IO_LOC "DIGIT[0]" K17; // 1.1 +IO_LOC "DIGIT[1]" J17; // 1.2 +IO_LOC "DIGIT[2]" L14; // 1.3 +IO_LOC "DIGIT[3]" L15; // 1.4 +IO_LOC "DIGIT[4]" L16; // 2.1 +IO_LOC "DIGIT[5]" M16; // 2.2 +IO_LOC "DIGIT[6]" H20; // 2.3 +IO_LOC "DIGIT[7]" G20; // 2.4 + +// GPIO +IO_LOC "GPIO[0]" B22; // 9 +IO_LOC "GPIO[1]" B21; // 10 +IO_LOC "GPIO[2]" A21; // 11 +IO_LOC "GPIO[4]" A20; // 13 +IO_LOC "GPIO[6]" B18; // 15 +IO_LOC "GPIO[16]" E21; // 5 +IO_LOC "GPIO[17]" G21; // 6 +IO_LOC "GPIO[18]" D21; // 7 +IO_LOC "GPIO[19]" G22; // 8 + +// Microphone +IO_LOC "GPIO[15]" A13; // 24 ws +IO_LOC "GPIO[13]" A14; // 22 lr +IO_LOC "GPIO[11]" A15; // 20 sck +IO_LOC "GPIO[9]" A16; // 18 sd +IO_PORT "GPIO[9]" PULL_MODE=DOWN; + +// Sound DAC +IO_LOC "GPIO[14]" B13; // 23 lrck +IO_LOC "GPIO[12]" B15; // 21 din +IO_LOC "GPIO[10]" B16; // 19 bck +IO_LOC "GPIO[8]" B17; // 17 sck + +// TM1638 +IO_LOC "GPIO[7]" A18; // 16 sio_stb +IO_LOC "GPIO[5]" A19; // 14 sio_clk +IO_LOC "GPIO[3]" B20; // 12 sio_data \ No newline at end of file diff --git a/boards/orangepi_msoc/board_specific.sdc b/boards/orangepi_msoc/board_specific.sdc new file mode 100644 index 00000000..bc3c3e22 --- /dev/null +++ b/boards/orangepi_msoc/board_specific.sdc @@ -0,0 +1,3 @@ +# The timing constraints + +create_clock -name CLK -period 40 -waveform {0 20} [get_ports {CLK}] diff --git a/boards/orangepi_msoc/board_specific.tcl b/boards/orangepi_msoc/board_specific.tcl new file mode 100644 index 00000000..e65db85f --- /dev/null +++ b/boards/orangepi_msoc/board_specific.tcl @@ -0,0 +1,10 @@ +# Synthesis and Place & Route settings + +set_device GW5AT-LV138PG484AC1/I0 -name GW5AT-138B -device_version B +set_option -synthesis_tool gowinsynthesis +set_option -output_base_name fpga_project +set_option -top_module board_specific_top +set_option -verilog_std sysv2017 + +set_option -use_cpu_as_gpio 1 +set_option -use_sspi_as_gpio 1 diff --git a/boards/orangepi_msoc/board_specific_top.sv b/boards/orangepi_msoc/board_specific_top.sv new file mode 100644 index 00000000..8a808465 --- /dev/null +++ b/boards/orangepi_msoc/board_specific_top.sv @@ -0,0 +1,257 @@ +`define FORCE_NO_INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE +`include "config.svh" +`include "lab_specific_board_config.svh" +`include "swap_bits.svh" + +`ifdef FORCE_NO_INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE + `undef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE +`endif + +module board_specific_top +# ( + parameter clk_mhz = 25, + + w_key = 4, + w_sw = 16, + w_led = 16, + w_digit = 8, + w_gpio = 20, + + screen_width = 800, + screen_height = 480, + + w_red = 5, + w_green = 6, + w_blue = 5, + + w_x = $clog2 ( screen_width ), + w_y = $clog2 ( screen_height ), + + w_sound = 16 +) +( + input CLK, + + input [w_key - 1:0] KEY, + input [w_sw - 1:0] SW, + + input UART_RX, + output UART_TX, + + output [w_led - 1:0] LED, + + output [ 7:0] HGFEDCBA, + output [w_digit - 1:0] DIGIT, + + inout [w_gpio - 1:0] GPIO +); + + wire clk = CLK; + + //------------------------------------------------------------------------ + + localparam w_tm_key = 8, + w_tm_led = 8, + w_tm_digit = 8, + right = 0; + + //------------------------------------------------------------------------ + + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE + + localparam w_lab_key = w_tm_key, + w_lab_sw = w_sw, + w_lab_led = w_tm_led, + w_lab_digit = w_tm_digit; + + `else // TM1638 module is not connected + + localparam w_lab_key = w_key, + w_lab_sw = w_sw, + w_lab_led = w_led, + w_lab_digit = w_digit; + + `endif + + //------------------------------------------------------------------------ + + wire [w_tm_key - 1:0] tm_key; + wire [w_tm_led - 1:0] tm_led; + wire [w_tm_digit - 1:0] tm_digit; + + logic [w_lab_key - 1:0] lab_key; + wire [w_lab_led - 1:0] lab_led; + wire [w_lab_digit - 1:0] lab_digit; + + wire rst; + wire [ 7:0] abcdefgh; + + wire [w_x - 1:0] x; + wire [w_y - 1:0] y; + + wire [ 23:0] mic; + wire [w_sound - 1:0] sound; + + //------------------------------------------------------------------------ + + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE + + assign rst = tm_key [w_tm_key - 1]; + assign lab_key = tm_key [w_tm_key - 1:0]; + + assign tm_led = lab_led; + assign tm_digit = lab_digit; + + assign LED = w_led' (~ lab_led); + + `else // TM1638 module is not connected + + assign rst = ~ KEY [w_key - 1]; + assign lab_key = ~ KEY [w_key - 1:0]; + + assign LED = lab_led; + + `endif + + //------------------------------------------------------------------------ + + wire slow_clk; + + slow_clk_gen # (.fast_clk_mhz (clk_mhz), .slow_clk_hz (1)) + i_slow_clk_gen (.slow_clk (slow_clk), .*); + + //------------------------------------------------------------------------ + + wire [w_x - 1:0] mirrored_x = w_x' (screen_width - 1 - x); + wire [w_y - 1:0] mirrored_y = w_y' (screen_height - 1 - y); + + //------------------------------------------------------------------------ + + lab_top + # ( + .clk_mhz ( clk_mhz ), + + .w_key ( w_lab_key ), // The last key is used for a reset + .w_sw ( w_lab_key ), + .w_led ( w_lab_led ), + .w_digit ( w_lab_digit ), + .w_gpio ( w_gpio ), + + .screen_width ( screen_width ), + .screen_height ( screen_height ), + + .w_red ( w_red ), + .w_green ( w_green ), + .w_blue ( w_blue ) + ) + i_lab_top + ( + .clk ( clk ), + .slow_clk ( slow_clk ), + .rst ( rst ), + + .key ( lab_key ), + .sw ( lab_sw ), + + .led ( lab_led ), + + .abcdefgh ( abcdefgh ), + .digit ( lab_digit ), + + .x ( mirrored_x ), + .y ( mirrored_y ), + + .red ( LCD_R ), + .green ( LCD_G ), + .blue ( LCD_B ), + + .uart_rx ( UART_RX ), + .uart_tx ( UART_TX ), + + .mic ( mic ), + .sound ( sound ), + + .gpio ( ) + ); + + //------------------------------------------------------------------------ + + wire [$left (abcdefgh):0] hgfedcba; + `SWAP_BITS (hgfedcba, abcdefgh); + + assign HGFEDCBA = ~ hgfedcba; + assign DIGIT = lab_digit; + + //------------------------------------------------------------------------ + + `ifdef INSTANTIATE_TM1638_BOARD_CONTROLLER_MODULE + + tm1638_board_controller + # ( + .clk_mhz ( clk_mhz ), + .w_digit ( w_tm_digit ) + ) + i_tm1638 + ( + .clk ( clk ), + .rst ( rst ), + .hgfedcba ( hgfedcba ), + .digit ( tm_digit ), + .ledr ( tm_led ), + .keys ( tm_key ), + .sio_data ( GPIO[3] ), + .sio_clk ( GPIO[5] ), + .sio_stb ( GPIO[7] ) + ); + + `endif + + //------------------------------------------------------------------------ + + `ifdef INSTANTIATE_MICROPHONE_INTERFACE_MODULE + + inmp441_mic_i2s_receiver_alt + # ( + .clk_mhz ( clk_mhz ) + ) + i_microphone + ( + .clk ( clk ), + .rst ( rst ), + .right ( right ), + .lr ( GPIO[13] ), + .ws ( GPIO[15] ), + .sck ( GPIO[11] ), + .sd ( GPIO[9] ), + .value ( mic ) + ); + + `endif + + //------------------------------------------------------------------------ + + `ifdef INSTANTIATE_SOUND_OUTPUT_INTERFACE_MODULE + + // External DAC PCM5102A, Digilent Pmod AMP3, UDA1334A + + i2s_audio_out + # ( + .clk_mhz ( clk_mhz ), + .in_res ( w_sound ), + .align_right ( 1'b0 ), + .offset_by_one_cycle ( 1'b1 ) + ) + i_ext_audio_out + ( + .clk ( clk ), + .reset ( rst ), + .data_in ( sound ), + .mclk ( GPIO[8] ), + .bclk ( GPIO[10] ), + .lrclk ( GPIO[14] ), + .sdata ( GPIO[12] ) + ); + + `endif + +endmodule diff --git a/boards/orangepi_msoc/fpga_project_01.gprj b/boards/orangepi_msoc/fpga_project_01.gprj new file mode 100644 index 00000000..36ab17fc --- /dev/null +++ b/boards/orangepi_msoc/fpga_project_01.gprj @@ -0,0 +1,7 @@ + + + + + 5 + gw5at138b-012 + diff --git a/boards/orangepi_msoc/fpga_project_02.gprj b/boards/orangepi_msoc/fpga_project_02.gprj new file mode 100644 index 00000000..8c6b9904 --- /dev/null +++ b/boards/orangepi_msoc/fpga_project_02.gprj @@ -0,0 +1,2 @@ + + diff --git a/boards/orangepi_msoc/project_process_config_01.json b/boards/orangepi_msoc/project_process_config_01.json new file mode 100644 index 00000000..8b6c52aa --- /dev/null +++ b/boards/orangepi_msoc/project_process_config_01.json @@ -0,0 +1,32 @@ +{ + "Allow_Duplicate_Modules" : false, + "Annotated_Properties_for_Analyst" : true, + "BACKGROUND_PROGRAMMING" : "off", + "COMPRESS" : false, + "CRC_CHECK" : true, + "Clock_Conversion" : true, + "Clock_Route_Order" : 0, + "Correct_Hold_Violation" : true, + "DONE" : true, + "DOWNLOAD_SPEED" : "default", + "Default_Enum_Encoding" : "default", + "Disable_Insert_Pad" : false, + "ENCRYPTION_KEY" : false, + "ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000", + "FORMAT" : "binary", + "FSM Compiler" : true, + "Fanout_Guide" : 10000, + "Frequency" : "Auto", + "Generate_Constraint_File_of_Ports" : false, + "Generate_IBIS_File" : false, + "Generate_Plain_Text_Timing_Report" : false, + "Generate_Post_PNR_Simulation_Model_File" : false, + "Generate_Post_Place_File" : false, + "Generate_SDF_File" : false, + "Generate_VHDL_Post_PNR_Simulation_Model_File" : false, + "GwSyn_Loop_Limit" : 2000, + "HOTBOOT" : false, + "I2C" : false, + "I2C_SLAVE_ADDR" : "00", + "Implicit_Initial_Value_Support" : false, + "IncludePath" : [ diff --git a/boards/orangepi_msoc/project_process_config_02.json b/boards/orangepi_msoc/project_process_config_02.json new file mode 100644 index 00000000..a861fbcd --- /dev/null +++ b/boards/orangepi_msoc/project_process_config_02.json @@ -0,0 +1,53 @@ + ], + "Incremental_Compile" : "", + "Initialize_Primitives" : false, + "JTAG" : false, + "MODE_IO" : false, + "MSPI" : false, + "Multiple_File_Compilation_Unit" : true, + "Number_of_Critical_Paths" : "", + "Number_of_Start/End_Points" : "", + "OUTPUT_BASE_NAME" : "fpga_project", + "POWER_ON_RESET_MONITOR" : true, + "PRINT_BSRAM_VALUE" : true, + "PROGRAM_DONE_BYPASS" : false, + "Pipelining" : true, + "PlaceInRegToIob" : true, + "PlaceIoRegToIob" : true, + "PlaceOutRegToIob" : true, + "Place_Option" : "0", + "Process_Configuration_Verion" : "1.0", + "Promote_Physical_Constraint_Warning_to_Error" : true, + "Push_Tristates" : true, + "READY" : true, + "RECONFIG_N" : false, + "Ram_RW_Check" : true, + "Report_Auto-Placed_Io_Information" : false, + "Resolve_Mixed_Drivers" : false, + "Resource_Sharing" : true, + "Retiming" : false, + "Route_Maxfan" : 23, + "Route_Option" : "0", + "Run_Timing_Driven" : true, + "SECURE_MODE" : false, + "SECURITY_BIT" : true, + "SPI_FLASH_ADDR" : "00000000", + "SSPI" : true, + "Show_All_Warnings" : false, + "Synthesis On/Off Implemented as Translate On/Off" : false, + "Synthesize_tool" : "GowinSyn", + "TclPre" : "", + "TopModule" : "board_specific_top", + "USERCODE" : "default", + "Unused_Pin" : "As_input_tri_stated_with_pull_up", + "Update_Compile_Point_Timing_Data" : false, + "Use_Clock_Period_for_Unconstrainted IO" : false, + "VCCAUX" : 3.3, + "VHDL_Standard" : "VHDL_Std_1993", + "Verilog_Standard" : "Vlg_Std_Sysv2017", + "WAKE_UP" : "0", + "Write_Vendor_Constraint_File" : true, + "dsp_balance" : false, + "show_all_warnings" : false, + "turn_off_bg" : false +} diff --git a/scripts/admin/generate_all_packages.bash b/scripts/admin/generate_all_packages.bash index 8d193f87..288150d2 100755 --- a/scripts/admin/generate_all_packages.bash +++ b/scripts/admin/generate_all_packages.bash @@ -58,6 +58,7 @@ update_fpga_toolchain_var () tang_primer_25k_dock* | \ tang_mega_138k_dock* | \ tang_mega_138k_pro_dock* | \ + orangepi* ) fpga_toolchain=gowin ;; diff --git a/scripts/steps/00_setup.source_bash b/scripts/steps/00_setup.source_bash index 09d569c1..4ff0c20f 100644 --- a/scripts/steps/00_setup.source_bash +++ b/scripts/steps/00_setup.source_bash @@ -323,7 +323,8 @@ update_fpga_toolchain_var () runber | \ marsohod3gw2* | \ - tang_* ) + tang_* | \ + orangepi* ) fpga_toolchain=gowin ;;