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| 1 | +.. zephyr:board:: max32660evsys |
| 2 | +
|
| 3 | +Overview |
| 4 | +******** |
| 5 | +The MAX32660 evaluation system offers a compact development platform that |
| 6 | +provides access to all the features of the MAX32660 in a tiny, easy to |
| 7 | +use board. A MAX32625PICO-based debug adapter comes attached to the main |
| 8 | +board. It can be snapped free when programming is complete. The debug |
| 9 | +module supports an optional 10-pin Arm® Cortex® debug connector for DAPLink |
| 10 | +functionality. Combined measurements are 0.65in x 2.2in, while the main board |
| 11 | +alone measures 0.65in x 0.95in. External connections terminate in a dual-row |
| 12 | +header footprint compatible with both thru-hole and SMT applications. This |
| 13 | +board provides a powerful processing subsystem in a very small space that |
| 14 | +can be easily integrated into a variety of applications. |
| 15 | + |
| 16 | +The Zephyr port is running on the MAX32660 MCU. |
| 17 | + |
| 18 | +.. image:: img/max32660evsys.webp |
| 19 | + :align: center |
| 20 | + :alt: MAX32660 EVSYS |
| 21 | + |
| 22 | +Hardware |
| 23 | +******** |
| 24 | + |
| 25 | +- MAX32660 MCU: |
| 26 | + |
| 27 | + - High-Efficiency Microcontroller for Wearable Devices |
| 28 | + - Internal Oscillator Operates Up to 96MHz |
| 29 | + - 256KB Flash Memory |
| 30 | + - 96KB SRAM, Optionally Preserved in Lowest Power Backup Mode |
| 31 | + - 16KB Instruction Cache |
| 32 | + - Memory Protection Unit (MPU) |
| 33 | + - Low 1.1V VCORE Supply Voltage |
| 34 | + - 3.6V GPIO Operating Range |
| 35 | + - Internal LDO Provides Operation from Single Supply |
| 36 | + - Wide Operating Temperature: -40°C to +105°C |
| 37 | + |
| 38 | + - Power Management Maximizes Uptime for Battery Applications |
| 39 | + - 85µA/MHz Active Executing from Flash |
| 40 | + - 2µA Full Memory Retention Power in Backup Mode at VDD = 1.8V |
| 41 | + - 450nA Ultra-Low Power RTC at VDD=1.8V |
| 42 | + - Internal 80kHz Ring Oscillator |
| 43 | + |
| 44 | + - Optimal Peripheral Mix Provides Platform Scalability |
| 45 | + - Up to 14 General-Purpose I/O Pins |
| 46 | + - Up to Two SPI |
| 47 | + - I2S |
| 48 | + - Up to Two UARTs |
| 49 | + - Up to Two I2C, 3.4Mbps High Speed |
| 50 | + - Four-Channel Standard DMA Controller |
| 51 | + - Three 32-Bit Timers |
| 52 | + - Watchdog Timer |
| 53 | + - CMOS-Level 32.768kHz RTC Output |
| 54 | + |
| 55 | +- Benefits and Features of MAX32660-EVSYS: |
| 56 | + |
| 57 | + - DIP Breakout Board |
| 58 | + - 100mil Pitch Dual Inline Pin Headers |
| 59 | + - Breadboard Compatible |
| 60 | + |
| 61 | + - Integrated Peripherals |
| 62 | + - Red Indicator LED |
| 63 | + - User Pushbutton |
| 64 | + |
| 65 | + - MAX32625PICO-Based Debug Adapter |
| 66 | + - CMSIS-DAP SWD Debugger |
| 67 | + - Virtual UART Console |
| 68 | + |
| 69 | +Supported Features |
| 70 | +================== |
| 71 | + |
| 72 | +The ``max32660evsys`` board supports the following interfaces: |
| 73 | + |
| 74 | ++-----------+------------+-------------------------------------+ |
| 75 | +| Interface | Controller | Driver/Component | |
| 76 | ++===========+============+=====================================+ |
| 77 | +| NVIC | on-chip | nested vector interrupt controller | |
| 78 | ++-----------+------------+-------------------------------------+ |
| 79 | +| SYSTICK | on-chip | systick | |
| 80 | ++-----------+------------+-------------------------------------+ |
| 81 | +| CLOCK | on-chip | clock and reset control | |
| 82 | ++-----------+------------+-------------------------------------+ |
| 83 | +| GPIO | on-chip | gpio | |
| 84 | ++-----------+------------+-------------------------------------+ |
| 85 | +| UART | on-chip | serial | |
| 86 | ++-----------+------------+-------------------------------------+ |
| 87 | + |
| 88 | +Programming and Debugging |
| 89 | +************************* |
| 90 | + |
| 91 | +Flashing |
| 92 | +======== |
| 93 | + |
| 94 | +An Arm® debug access port (DAP) provides an external interface for debugging during application |
| 95 | +development. The DAP is a standard Arm CoreSight® serial wire debug port, uses a two-pin serial |
| 96 | +interface (SWDCLK and SWDIO), and is accessed through 10-pin header (J4). |
| 97 | + |
| 98 | +Once the debug probe is connected to your host computer, then you can simply run the |
| 99 | +``west flash`` command to write a firmware image into flash. |
| 100 | + |
| 101 | +.. note:: |
| 102 | + |
| 103 | + This board uses OpenOCD as the default debug interface. You can also use |
| 104 | + a Segger J-Link with Segger's native tooling by overriding the runner, |
| 105 | + appending ``--runner jlink`` to your ``west`` command(s). The J-Link should |
| 106 | + be connected to the standard 2*5 pin debug connector (J3) using an |
| 107 | + appropriate adapter board and cable. |
| 108 | + |
| 109 | +Debugging |
| 110 | +========= |
| 111 | + |
| 112 | +Please refer to the `Flashing`_ section and run the ``west debug`` command |
| 113 | +instead of ``west flash``. |
| 114 | + |
| 115 | +References |
| 116 | +********** |
| 117 | + |
| 118 | +- `MAX32660EVSYS web page`_ |
| 119 | + |
| 120 | +.. _MAX32660EVSYS web page: |
| 121 | + https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32660-evsys.html |
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