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drivers: pwm: sf32lb: add atim based pwm driver
add atim based pwm driver for sf32lb platform Signed-off-by: Qingsong Gou <[email protected]>
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‎drivers/pwm/CMakeLists.txt‎

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@@ -58,6 +58,7 @@ zephyr_library_sources_ifdef(CONFIG_PWM_RV32M1_TPM pwm_rv32m1_tpm.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_SAM pwm_sam.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_SAM0_TC pwm_sam0_tc.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_SAM0_TCC pwm_sam0_tcc.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_SF32LB_ATIM pwm_sf32lb_atim.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_SF32LB_GPT pwm_sf32lb_gpt.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_SIFIVE pwm_sifive.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_SILABS_LETIMER pwm_silabs_letimer.c)

‎drivers/pwm/Kconfig.sf32lb‎

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@@ -8,3 +8,11 @@ config PWM_SF32LB_GPT
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help
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Enable PWM driver for SF32LB series of MCUs. This driver uses
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the timer peripheral to implement PWM functionality.
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config PWM_SF32LB_ATIM
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bool "ATIM based PWM driver for SF32LB family of MCUs"
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default y
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depends on DT_HAS_SIFLI_SF32LB_ATIM_PWM_ENABLED
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help
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Enable PWM driver for SF32LB series of MCUs. This driver uses
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the advanced timer peripheral to implement PWM functionality.

‎drivers/pwm/pwm_sf32lb_atim.c‎

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/*
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* Copyright (c) 2025, Qingsong Gou <[email protected]>
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT sifli_sf32lb_atim_pwm
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#include <zephyr/drivers/pwm.h>
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#include <zephyr/drivers/clock_control/sf32lb.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/kernel.h>
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#include <zephyr/logging/log.h>
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#include <register.h>
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LOG_MODULE_REGISTER(pwm_sf32lb_atim, CONFIG_PWM_LOG_LEVEL);
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#define CR1 offsetof(ATIM_TypeDef, CR1)
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#define CR2 offsetof(ATIM_TypeDef, CR2)
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#define DIER offsetof(ATIM_TypeDef, DIER)
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#define SR offsetof(ATIM_TypeDef, SR)
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#define EGR offsetof(ATIM_TypeDef, EGR)
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#define CCMR1 offsetof(ATIM_TypeDef, CCMR1)
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#define CCMR2 offsetof(ATIM_TypeDef, CCMR2)
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#define CCER offsetof(ATIM_TypeDef, CCER)
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#define PSC offsetof(ATIM_TypeDef, PSC)
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#define ARR offsetof(ATIM_TypeDef, ARR)
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#define CCR1 offsetof(ATIM_TypeDef, CCR1)
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#define CCR2 offsetof(ATIM_TypeDef, CCR2)
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#define CCR3 offsetof(ATIM_TypeDef, CCR3)
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#define CCR4 offsetof(ATIM_TypeDef, CCR4)
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#define BDTR offsetof(ATIM_TypeDef, BDTR)
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#define ATIM_PWM_MODE1 (6U)
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#define CCMRX(ch) ((ch) <= 1 ? CCMR1 : CCMR2)
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#define MAX_CH_NUM (4U)
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struct pwm_sf32lb_atim_config {
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uintptr_t base;
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const struct pinctrl_dev_config *pincfg;
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struct sf32lb_clock_dt_spec clock;
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uint32_t prescaler;
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};
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static int pwm_sf32lb_atim_set_cycles(const struct device *dev, uint32_t channel,
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uint32_t period_cycles, uint32_t pulse_cycles,
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pwm_flags_t flags)
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{
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const struct pwm_sf32lb_atim_config *cfg = dev->config;
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uint32_t ccmr;
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if (channel >= MAX_CH_NUM) {
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return -EINVAL;
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}
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/* disable the channel */
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sys_clear_bit(cfg->base + CCER, channel * 4);
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sys_write32(period_cycles - 1, cfg->base + ARR);
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switch (channel) {
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case 0:
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sys_write32(pulse_cycles, cfg->base + CCR1);
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ccmr = sys_read32(cfg->base + CCMRX(channel));
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ccmr &= ~ATIM_CCMR1_OC1M_Msk;
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ccmr |= FIELD_PREP(ATIM_CCMR1_OC1M_Msk, ATIM_PWM_MODE1);
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ccmr |= ATIM_CCMR1_OC1PE;
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sys_write32(ccmr, cfg->base + CCMRX(channel));
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break;
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case 1:
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sys_write32(pulse_cycles, cfg->base + CCR2);
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ccmr = sys_read32(cfg->base + CCMRX(channel));
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ccmr &= ~ATIM_CCMR1_OC2M_Msk;
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ccmr |= FIELD_PREP(ATIM_CCMR1_OC2M_Msk, ATIM_PWM_MODE1);
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ccmr |= ATIM_CCMR1_OC2PE;
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sys_write32(ccmr, cfg->base + CCMRX(channel));
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break;
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case 2:
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sys_write32(pulse_cycles, cfg->base + CCR3);
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ccmr = sys_read32(cfg->base + CCMRX(channel));
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ccmr &= ~ATIM_CCMR2_OC3M_Msk;
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ccmr |= FIELD_PREP(ATIM_CCMR2_OC3M_Msk, ATIM_PWM_MODE1);
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ccmr |= ATIM_CCMR2_OC3PE;
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sys_write32(ccmr, cfg->base + CCMRX(channel));
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break;
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case 3:
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sys_write32(pulse_cycles, cfg->base + CCR4);
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ccmr = sys_read32(cfg->base + CCMRX(channel));
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ccmr &= ~ATIM_CCMR2_OC4M_Msk;
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ccmr |= FIELD_PREP(ATIM_CCMR2_OC4M_Msk, ATIM_PWM_MODE1);
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ccmr |= ATIM_CCMR2_OC4PE;
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sys_write32(ccmr, cfg->base + CCMRX(channel));
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break;
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default:
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return -EINVAL;
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}
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if (flags & PWM_POLARITY_INVERTED) {
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sys_set_bit(cfg->base + CCER, channel * 4 + 1);
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}
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/* enable the channel */
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sys_set_bit(cfg->base + CCER, channel * 4);
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return 0;
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}
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static int pwm_sf32lb_atim_get_cycles_per_sec(const struct device *dev, uint32_t channel,
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uint64_t *cycles)
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{
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const struct pwm_sf32lb_atim_config *cfg = dev->config;
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uint32_t clk_rate;
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if (sf32lb_clock_control_get_rate_dt(&cfg->clock, &clk_rate)) {
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return -EIO;
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}
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*cycles = clk_rate / (cfg->prescaler + 1);
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printk("clk_rate: %d, prescaler: %d, cycles: %lld\n", clk_rate, cfg->prescaler, *cycles);
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return 0;
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}
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static const struct pwm_driver_api pwm_sf32lb_atim_api = {
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.set_cycles = pwm_sf32lb_atim_set_cycles,
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.get_cycles_per_sec = pwm_sf32lb_atim_get_cycles_per_sec,
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};
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static int pwm_sf32lb_atim_init(const struct device *dev)
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{
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const struct pwm_sf32lb_atim_config *cfg = dev->config;
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int err;
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err = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_DEFAULT);
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if (err < 0) {
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return err;
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}
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if (!sf32lb_clock_is_ready_dt(&cfg->clock)) {
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return -ENODEV;
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}
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err = sf32lb_clock_control_on_dt(&cfg->clock);
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if (err < 0) {
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return err;
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}
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sys_write32(cfg->prescaler, cfg->base + PSC);
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sys_set_bit(cfg->base + EGR, ATIM_EGR_UG_Pos);
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/* enable auto-reload preload */
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sys_set_bit(cfg->base + CR1, ATIM_CR1_ARPE_Pos);
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/* enable timer */
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sys_set_bit(cfg->base + CR1, ATIM_CR1_CEN_Pos);
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sys_set_bit(cfg->base + BDTR, ATIM_BDTR_MOE_Pos);
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return err;
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}
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#define PWM_SF32LB_ATIM_DEFINE(n) \
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PINCTRL_DT_INST_DEFINE(n); \
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static const struct pwm_sf32lb_atim_config pwm_sf32lb_atim_config_##n = { \
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.base = DT_REG_ADDR(DT_INST_PARENT(n)), \
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.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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.clock = SF32LB_CLOCK_DT_INST_PARENT_SPEC_GET(n), \
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.prescaler = DT_PROP(DT_INST_PARENT(n), sifli_prescaler), \
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}; \
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DEVICE_DT_INST_DEFINE(n, pwm_sf32lb_atim_init, NULL, NULL, \
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&pwm_sf32lb_atim_config_##n, POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \
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&pwm_sf32lb_atim_api);
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DT_INST_FOREACH_STATUS_OKAY(PWM_SF32LB_ATIM_DEFINE)

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