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soc: adi: Add MAX32660 SoC
This commit adds MAX32660 SoC and dts files. Signed-off-by: Yasin Ustuner <[email protected]>
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‎dts/arm/adi/max32/max32660-pinctrl.dtsi

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/*
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* Copyright (c) 2025 Analog Devices, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/pinctrl/max32-pinctrl.h>
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/ {
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soc {
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pinctrl: pin-controller@40008000 {
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/omit-if-no-ref/ swdio_p0_0: swdio_p0_0 {
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pinmux = <MAX32_PINMUX(0, 0, AF1)>;
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};
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/omit-if-no-ref/ spi1_miso_p0_0: spi1_miso_p0_0 {
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pinmux = <MAX32_PINMUX(0, 0, AF2)>;
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};
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/omit-if-no-ref/ uart1_tx_p0_0: uart1_tx_p0_0 {
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pinmux = <MAX32_PINMUX(0, 0, AF3)>;
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};
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/omit-if-no-ref/ swdclk_p0_1: swdclk_p0_1 {
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pinmux = <MAX32_PINMUX(0, 1, AF1)>;
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};
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/omit-if-no-ref/ spi1_mosi_p0_1: spi1_mosi_p0_1 {
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pinmux = <MAX32_PINMUX(0, 1, AF2)>;
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};
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/omit-if-no-ref/ uart1_rx_p0_1: uart1_rx_p0_1 {
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pinmux = <MAX32_PINMUX(0, 1, AF3)>;
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};
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/omit-if-no-ref/ i2c1_scl_p0_2: i2c1_scl_p0_2 {
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pinmux = <MAX32_PINMUX(0, 2, AF1)>;
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};
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/omit-if-no-ref/ spi1_sck_p0_2: spi1_sck_p0_2 {
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pinmux = <MAX32_PINMUX(0, 2, AF2)>;
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};
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/omit-if-no-ref/ cal32k_p0_2: cal32k_p0_2 {
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pinmux = <MAX32_PINMUX(0, 2, AF3)>;
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};
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/omit-if-no-ref/ i2c1_sda_p0_3: i2c1_sda_p0_3 {
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pinmux = <MAX32_PINMUX(0, 3, AF1)>;
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};
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/omit-if-no-ref/ spi1_ss0_p0_3: spi1_ss0_p0_3 {
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pinmux = <MAX32_PINMUX(0, 3, AF2)>;
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};
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/omit-if-no-ref/ tmr0_p0_3: tmr0_p0_3 {
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pinmux = <MAX32_PINMUX(0, 3, AF3)>;
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};
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/omit-if-no-ref/ spi0_miso_p0_4: spi0_miso_p0_4 {
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pinmux = <MAX32_PINMUX(0, 4, AF1)>;
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};
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/omit-if-no-ref/ uart0_tx_p0_4: uart0_tx_p0_4 {
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pinmux = <MAX32_PINMUX(0, 4, AF2)>;
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};
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/omit-if-no-ref/ spi0_mosi_p0_5: spi0_mosi_p0_5 {
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pinmux = <MAX32_PINMUX(0, 5, AF1)>;
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};
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/omit-if-no-ref/ uart0_rx_p0_5: uart0_rx_p0_5 {
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pinmux = <MAX32_PINMUX(0, 5, AF2)>;
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};
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/omit-if-no-ref/ spi0_sck_p0_6: spi0_sck_p0_6 {
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pinmux = <MAX32_PINMUX(0, 6, AF1)>;
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};
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/omit-if-no-ref/ uart0_cts_p0_6: uart0_cts_p0_6 {
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pinmux = <MAX32_PINMUX(0, 6, AF2)>;
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};
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/omit-if-no-ref/ uart1_tx_p0_6: uart1_tx_p0_6 {
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pinmux = <MAX32_PINMUX(0, 6, AF3)>;
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};
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/omit-if-no-ref/ spi0_ss0_p0_7: spi0_ss0_p0_7 {
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pinmux = <MAX32_PINMUX(0, 7, AF1)>;
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};
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/omit-if-no-ref/ uart0_rts_p0_7: uart0_rts_p0_7 {
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pinmux = <MAX32_PINMUX(0, 7, AF2)>;
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};
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/omit-if-no-ref/ uart1_rx_p0_7: uart1_rx_p0_7 {
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pinmux = <MAX32_PINMUX(0, 7, AF3)>;
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};
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/omit-if-no-ref/ i2c0_scl_p0_8: i2c0_scl_p0_8 {
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pinmux = <MAX32_PINMUX(0, 8, AF1)>;
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};
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/omit-if-no-ref/ swdio_p0_8: swdio_p0_8 {
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pinmux = <MAX32_PINMUX(0, 8, AF2)>;
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};
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/omit-if-no-ref/ i2c0_sda_p0_9: i2c0_sda_p0_9 {
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pinmux = <MAX32_PINMUX(0, 9, AF1)>;
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};
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/omit-if-no-ref/ swdclk_p0_9: swdclk_p0_9 {
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pinmux = <MAX32_PINMUX(0, 9, AF2)>;
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};
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/omit-if-no-ref/ spi1_miso_p0_10: spi1_miso_p0_10 {
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pinmux = <MAX32_PINMUX(0, 10, AF1)>;
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};
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/omit-if-no-ref/ uart1_tx_p0_10: uart1_tx_p0_10 {
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pinmux = <MAX32_PINMUX(0, 10, AF2)>;
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};
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/omit-if-no-ref/ spi1_mosi_p0_11: spi1_mosi_p0_11 {
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pinmux = <MAX32_PINMUX(0, 11, AF1)>;
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};
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/omit-if-no-ref/ uart1_rx_p0_11: uart1_rx_p0_11 {
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pinmux = <MAX32_PINMUX(0, 11, AF2)>;
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};
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/omit-if-no-ref/ spi1_sck_p0_12: spi1_sck_p0_12 {
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pinmux = <MAX32_PINMUX(0, 12, AF1)>;
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};
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/omit-if-no-ref/ uart1_cts_p0_12: uart1_cts_p0_12 {
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pinmux = <MAX32_PINMUX(0, 12, AF2)>;
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};
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/omit-if-no-ref/ spi1_ss0_p0_13: spi1_ss0_p0_13 {
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pinmux = <MAX32_PINMUX(0, 13, AF1)>;
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};
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/omit-if-no-ref/ uart1_rts_p0_13: uart1_rts_p0_13 {
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pinmux = <MAX32_PINMUX(0, 13, AF2)>;
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};
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};
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};
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};

‎dts/arm/adi/max32/max32660.dtsi

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/*
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* Copyright (c) 2025 Analog Devices, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <adi/max32/max32xxx.dtsi>
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&clk_ipo {
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clock-frequency = <DT_FREQ_M(96)>;
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};
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&flash0 {
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reg = <0x00000000 DT_SIZE_K(256)>;
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};
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&sram0 {
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reg = <0x20000000 DT_SIZE_K(16)>;
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};
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/delete-node/ &clk_iso;
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/delete-node/ &clk_ibro;
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/delete-node/ &clk_erfo;
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/delete-node/ &adc;
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/delete-node/ &gpio1;
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/delete-node/ &i2c2;
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/delete-node/ &uart2;
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/delete-node/ &timer3;
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/delete-node/ &trng;
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/* MAX32660 extra peripherals. */
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/ {
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chosen {
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zephyr,entropy = &{/}; /* Assigns an invalid node */
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};
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soc {
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sram1: memory@20004000 {
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compatible = "mmio-sram";
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reg = <0x20004000 DT_SIZE_K(16)>;
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};
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sram2: memory@20008000 {
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compatible = "mmio-sram";
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reg = <0x20008000 DT_SIZE_K(32)>;
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};
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sram3: memory@20010000 {
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compatible = "mmio-sram";
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reg = <0x20010000 DT_SIZE_K(32)>;
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};
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dma0: dma@40028000 {
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compatible = "adi,max32-dma";
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reg = <0x40028000 0x1000>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>;
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interrupts = <28 0>, <29 0>, <30 0>, <31 0>;
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dma-channels = <4>;
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status = "disabled";
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#dma-cells = <2>;
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};
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spi0: spi@40046000 {
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compatible = "adi,max32-spi";
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reg = <0x40046000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS0 6>;
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interrupts = <16 0>;
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status = "disabled";
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};
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spi1: spi@40019000 {
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compatible = "adi,max32-spi";
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reg = <0x40019000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS0 7>;
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interrupts = <17 0>;
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status = "disabled";
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};
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};
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};

‎soc/adi/max32/Kconfig.defconfig.max32660

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# Analog Devices MAX32660 MCU
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# Copyright (c) 2025 Analog Devices, Inc.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_MAX32660
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,/clocks/clk_ipo,clock-frequency)
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config NUM_IRQS
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default 55
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endif # SOC_MAX32660

‎soc/adi/max32/Kconfig.soc

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@@ -21,6 +21,10 @@ config SOC_MAX32655_M4
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select SOC_MAX32655
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select SOC_FAMILY_MAX32_M4
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config SOC_MAX32660
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bool
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select SOC_FAMILY_MAX32_M4
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config SOC_MAX32662
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bool
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select SOC_FAMILY_MAX32_M4
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config SOC
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default "max32655" if SOC_MAX32655
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default "max32660" if SOC_MAX32660
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default "max32662" if SOC_MAX32662
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default "max32666" if SOC_MAX32666
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default "max32670" if SOC_MAX32670

‎soc/adi/max32/soc.yml

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- name: max32655
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cpuclusters:
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- name: m4
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- name: max32660
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- name: max32662
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- name: max32666
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cpuclusters:

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