STM32 Zephyr 3.7.1-rc1 issue: E: Rx buffer should be placed in a nocache memory region

[RobMeades]

I am testing the move from Zephyr 3.6.0 to the 3.7.0-rc1 and our STM32F7 platform (which uses async UART, though that may not necessarily be relevant) throws a new error:

E: Rx buffer should be placed in a nocache memory region

...and afterwards random crashes occur in zephyr/drivers/serial/uart_stm32.c, the first one being ASSERTION FAIL [left_chunk(h, right_chunk(h, c)) == c] @ WEST_TOPDIR/zephyr/lib/heap/heap.c:183 - corrupted heap bounds (buffer overflow?) for memory at 0x2002abcc.

All our RX buffers are just malloc()ed RAM: can anyone point me at guidance as to what we need to change to make our code work for 3.7.0?

[ajarmouni-st]

Hi @RobMeades

which uses async UART, though that may not necessarily be relevant

In the contrary, it's quite relevant as you apparently have CONFIG_DCACHEenabled in your project & you are using DMA (async UART => UART with DMA), & since STM32 UART driver does not yet handle cache coherency by itself, it checks if the buffers provided by the application are in a non-cached memory region before performing any transfer.
This behavior was introduced in #70503

The solution would be to either disable DCACHE, or put your UART buffers in a Nocache memory region as done in tests/drivers/uart/uart_async_api/src/test_uart_async.c.

[RobMeades]

Hi, and thanks for the swift response. I haven't specifically enabled CONFIG_DCACHE in my project but, searching the Zephyr documentation for 3.7.0-rc1, I see that it is on by default.

Configuring looks frighteningly complicated; I will chicken out and disable it for now. Will confirm back here if that fixes things for me...

[RobMeades]

Confirmed that removes the error message, though a crash remains, now somewhere in the Zephyr heap, I will debug that separately.

E: ***** BUS FAULT *****
E:   Imprecise data bus error
E: r0/a1:  0x20028400  r1/a2:  0x00002dbf  r2/a3:  0x00003fff
E: r3/a4:  0x00003fff r12/ip:  0x200142e0 r14/lr:  0x0806adc1
E:  xpsr:  0x81000000
E: r4/v1:  0x20028400  r5/v2:  0x0000059b  r6/v3:  0x00002cd8
E: r7/v4:  0x2002b0d8  r8/v5:  0x00000000  r9/v6:  0x00000000
E: r10/v7: 0x00000000  r11/v8: 0x00000000    psp:  0x20051f08
E: EXC_RETURN: 0xfffffffd
E: Faulting instruction address (r15/pc): 0x0806aea6
E: >>> ZEPHYR FATAL ERROR 26: Unknown error on CPU 0
E: Current thread: 0x20021b90 (main)
### Dumping current thread (main) ###
    0x0806aea6: free_chunk                   /home/zephyr_native-v3.7.0-rc1/zephyr/lib/heap/heap.c:144 (discriminator 1)
    0x0806adbc: free_list_remove             /home/zephyr_native-v3.7.0-rc1/zephyr/lib/heap/heap.c:64
    0x08042e2c: sys_heap_free                /home/zephyr_native-v3.7.0-rc1/zephyr/lib/heap/heap.c:197
    0x08056bf6: k_heap_free                  /home/zephyr_native-v3.7.0-rc1/zephyr/kernel/kheap.c:153
    0x08077a96: k_free                       /home/zephyr_native-v3.7.0-rc1/zephyr/kernel/mempool.c:54

[zafersn]

Hi , I’m running into the same issue while working with the STM32U575 MCU. I followed your advice, @ajarmouni-st and checked out the file tests/drivers/uart/uart_async_api/src/test_uart_async.c.

#if defined(CONFIG_DCACHE) && defined(CONFIG_DT_DEFINED_NOCACHE)
#define __NOCACHE	__attribute__ ((__section__(CONFIG_DT_DEFINED_NOCACHE_NAME)))
#define NOCACHE_MEM 1

First thing I noticed: there’s no sample nocache region defined for the nucleo_u575zi_q board. So that specific case doesn’t really apply to me.

I also tried enabling CONFIG_NOCACHE_MEMORY, but couldn’t get it to work. something seems to be blocking it. I dug through the config files to look for dependencies and found that nocache_memory is only selected in zephyr/drivers/ethernet/Kconfig.stm32_hal, which doesn’t help with STM32 UART async.

Kept digging and saw that NOCACHE_MEMORY depends on ARCH_HAS_NOCACHE_MEMORY_SUPPORT in zephyr/arch/Kconfig, but I couldn’t find any specific support for STM32. Maybe STM gets this from CPU_CORTEX_M, but I’m not sure.

The only thing that worked for me was going into zephyr/soc/st/stm32/stm32u5x/Kconfig.defconfig and removing CONFIG_DCACHE=y. But obviously, that’s more of a hack than a proper solution.

Am I missing something? Is there a correct way to disable dcache and use a nocache region on STM32U575?