From 595b5b7b0a0871f6feb91f36f0594b6de6a4b5c7 Mon Sep 17 00:00:00 2001 From: Immo Birnbaum Date: Mon, 13 Jun 2022 09:08:38 +0200 Subject: [PATCH] soc: arm: xilinx_zynq7000: add MMU PTEs for all AXI GPIO IP core instances add the MMU page table entries for all instances of the Xilinx AXI GPIO controller IP core. Other than any Zynq-7000 peripheral supported so far, the existance of 1..n instances of the IP core within the FPGA part of the SoC is optional. Therefore, other than addressing instances of supported peripherals using their DT node label as has always been the case so far, the data for the MMU page table is added using the DT_FOREACH_STATUS_OKAY macro. Signed-off-by: Immo Birnbaum --- soc/arm/xilinx_zynq7000/xc7zxxx/soc.c | 7 +++++++ soc/arm/xilinx_zynq7000/xc7zxxxs/soc.c | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/soc.c b/soc/arm/xilinx_zynq7000/xc7zxxx/soc.c index d8e8a1a1d8346..1980dc5cdccdf 100644 --- a/soc/arm/xilinx_zynq7000/xc7zxxx/soc.c +++ b/soc/arm/xilinx_zynq7000/xc7zxxx/soc.c @@ -15,6 +15,11 @@ /* System Level Control Registers (SLCR) */ #define SLCR_UNLOCK 0x0008 #define SLCR_UNLOCK_KEY 0xdf0d +#define AXI_GPIO_MMU_ENTRY(id)\ + MMU_REGION_FLAT_ENTRY("axigpio",\ + DT_REG_ADDR(id),\ + DT_REG_SIZE(id),\ + MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W), static const struct arm_mmu_region mmu_regions[] = { @@ -68,6 +73,8 @@ static const struct arm_mmu_region mmu_regions[] = { MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W), #endif +DT_FOREACH_STATUS_OKAY(xlnx_xps_gpio_1_00_a, AXI_GPIO_MMU_ENTRY) + }; const struct arm_mmu_config mmu_config = { diff --git a/soc/arm/xilinx_zynq7000/xc7zxxxs/soc.c b/soc/arm/xilinx_zynq7000/xc7zxxxs/soc.c index bbb4b09f28396..66efc72150bc4 100644 --- a/soc/arm/xilinx_zynq7000/xc7zxxxs/soc.c +++ b/soc/arm/xilinx_zynq7000/xc7zxxxs/soc.c @@ -15,6 +15,11 @@ /* System Level Configuration Registers */ #define SLCR_UNLOCK 0x0008 #define SLCR_UNLOCK_KEY 0xdf0d +#define AXI_GPIO_MMU_ENTRY(id)\ + MMU_REGION_FLAT_ENTRY("axigpio",\ + DT_REG_ADDR(id),\ + DT_REG_SIZE(id),\ + MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W), static const struct arm_mmu_region mmu_regions[] = { @@ -68,6 +73,8 @@ static const struct arm_mmu_region mmu_regions[] = { MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W), #endif +DT_FOREACH_STATUS_OKAY(xlnx_xps_gpio_1_00_a, AXI_GPIO_MMU_ENTRY) + }; const struct arm_mmu_config mmu_config = {