diff --git a/boards/adi/max32660evsys/Kconfig.max32660evsys b/boards/adi/max32660evsys/Kconfig.max32660evsys new file mode 100644 index 000000000000..2e9363977615 --- /dev/null +++ b/boards/adi/max32660evsys/Kconfig.max32660evsys @@ -0,0 +1,7 @@ +# MAX32660EVSYS boards configuration + +# Copyright (c) 2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAX32660EVSYS + select SOC_MAX32660 diff --git a/boards/adi/max32660evsys/board.cmake b/boards/adi/max32660evsys/board.cmake new file mode 100644 index 000000000000..617eecca8f8e --- /dev/null +++ b/boards/adi/max32660evsys/board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/adi/max32660evsys/board.yml b/boards/adi/max32660evsys/board.yml new file mode 100644 index 000000000000..5e7e264b04c8 --- /dev/null +++ b/boards/adi/max32660evsys/board.yml @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: max32660evsys + full_name: MAX32660EVSYS + vendor: adi + socs: + - name: max32660 diff --git a/boards/adi/max32660evsys/doc/img/max32660evsys.webp b/boards/adi/max32660evsys/doc/img/max32660evsys.webp new file mode 100644 index 000000000000..b3043a033a24 Binary files /dev/null and b/boards/adi/max32660evsys/doc/img/max32660evsys.webp differ diff --git a/boards/adi/max32660evsys/doc/index.rst b/boards/adi/max32660evsys/doc/index.rst new file mode 100644 index 000000000000..91919764c297 --- /dev/null +++ b/boards/adi/max32660evsys/doc/index.rst @@ -0,0 +1,123 @@ +.. zephyr:board:: max32660evsys + +Overview +******** +The MAX32660 evaluation system offers a compact development platform that +provides access to all the features of the MAX32660 in a tiny, easy to +use board. A MAX32625PICO-based debug adapter comes attached to the main +board. It can be snapped free when programming is complete. The debug +module supports an optional 10-pin Arm® Cortex® debug connector for DAPLink +functionality. Combined measurements are 0.65in x 2.2in, while the main board +alone measures 0.65in x 0.95in. External connections terminate in a dual-row +header footprint compatible with both thru-hole and SMT applications. This +board provides a powerful processing subsystem in a very small space that +can be easily integrated into a variety of applications. + +The Zephyr port is running on the MAX32660 MCU. + +Hardware +******** + +- MAX32660 MCU: + + - High-Efficiency Microcontroller for Wearable Devices + + - Internal Oscillator Operates Up to 96MHz + - 256KB Flash Memory + - 96KB SRAM, Optionally Preserved in Lowest Power Backup Mode + - 16KB Instruction Cache + - Memory Protection Unit (MPU) + - Low 1.1V VCORE Supply Voltage + - 3.6V GPIO Operating Range + - Internal LDO Provides Operation from Single Supply + - Wide Operating Temperature: -40°C to +105°C + + - Power Management Maximizes Uptime for Battery Applications + + - 85µA/MHz Active Executing from Flash + - 2µA Full Memory Retention Power in Backup Mode at VDD = 1.8V + - 450nA Ultra-Low Power RTC at VDD=1.8V + - Internal 80kHz Ring Oscillator + + - Optimal Peripheral Mix Provides Platform Scalability + + - Up to 14 General-Purpose I/O Pins + - Up to Two SPI + - I2S + - Up to Two UARTs + - Up to Two I2C, 3.4Mbps High Speed + - Four-Channel Standard DMA Controller + - Three 32-Bit Timers + - Watchdog Timer + - CMOS-Level 32.768kHz RTC Output + +- Benefits and Features of MAX32660-EVSYS: + + - DIP Breakout Board + + - 100mil Pitch Dual Inline Pin Headers + - Breadboard Compatible + + - Integrated Peripherals + + - Red Indicator LED + - User Pushbutton + + - MAX32625PICO-Based Debug Adapter + + - CMSIS-DAP SWD Debugger + - Virtual UART Console + +Supported Features +================== + +The ``max32660evsys`` board supports the following interfaces: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock and reset control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ + +Programming and Debugging +************************* + +Flashing +======== + +An Arm® debug access port (DAP) provides an external interface for debugging during application +development. The DAP is a standard Arm CoreSight® serial wire debug port, uses a two-pin serial +interface (SWDCLK and SWDIO), and is accessed through 10-pin header (J4). + +Once the debug probe is connected to your host computer, then you can simply run the +``west flash`` command to write a firmware image into flash. + +.. note:: + + This board uses OpenOCD as the default debug interface. You can also use + a Segger J-Link with Segger's native tooling by overriding the runner, + appending ``--runner jlink`` to your ``west`` command(s). The J-Link should + be connected to the standard 2*5 pin debug connector (J3) using an + appropriate adapter board and cable. + +Debugging +========= + +Please refer to the `Flashing`_ section and run the ``west debug`` command +instead of ``west flash``. + +References +********** + +- `MAX32660EVSYS web page`_ + +.. _MAX32660EVSYS web page: + https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32660-evsys.html diff --git a/boards/adi/max32660evsys/max32660evsys.dts b/boards/adi/max32660evsys/max32660evsys.dts new file mode 100644 index 000000000000..f06645f94a1e --- /dev/null +++ b/boards/adi/max32660evsys/max32660evsys.dts @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + model = "Analog Devices MAX32660EVSYS"; + compatible = "adi,max32660evsys"; + + chosen { + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + zephyr,sram = &sram2; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + + led1: led_1 { + gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + label = "Red LED"; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led1; + }; + +}; + +&uart1 { + pinctrl-0 = <&uart1_tx_p0_10 &uart1_rx_p0_11>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +&clk_ipo { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; diff --git a/boards/adi/max32660evsys/max32660evsys.yaml b/boards/adi/max32660evsys/max32660evsys.yaml new file mode 100644 index 000000000000..da963ef091c6 --- /dev/null +++ b/boards/adi/max32660evsys/max32660evsys.yaml @@ -0,0 +1,13 @@ +identifier: max32660evsys +name: max32660evsys +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - serial +ram: 96 +flash: 256 diff --git a/boards/adi/max32660evsys/max32660evsys_defconfig b/boards/adi/max32660evsys/max32660evsys_defconfig new file mode 100644 index 000000000000..9428e5334a08 --- /dev/null +++ b/boards/adi/max32660evsys/max32660evsys_defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/common/openocd-adi-max32.boards.cmake b/boards/common/openocd-adi-max32.boards.cmake index 3f2c3829cf1a..2c65ce974e3f 100644 --- a/boards/common/openocd-adi-max32.boards.cmake +++ b/boards/common/openocd-adi-max32.boards.cmake @@ -10,6 +10,8 @@ if(CONFIG_SOC_MAX32650) set(MAX32_TARGET_CFG "max32650.cfg") elseif(CONFIG_SOC_MAX32655_M4) set(MAX32_TARGET_CFG "max32655.cfg") +elseif(CONFIG_SOC_MAX32660) + set(MAX32_TARGET_CFG "max32660.cfg") elseif(CONFIG_SOC_MAX32662) set(MAX32_TARGET_CFG "max32662.cfg") elseif(CONFIG_SOC_MAX32666) diff --git a/dts/arm/adi/max32/max32660-pinctrl.dtsi b/dts/arm/adi/max32/max32660-pinctrl.dtsi new file mode 100644 index 000000000000..cfb872c11d31 --- /dev/null +++ b/dts/arm/adi/max32/max32660-pinctrl.dtsi @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + soc { + pinctrl: pin-controller@40008000 { + /omit-if-no-ref/ swdio_p0_0: swdio_p0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ spi1_miso_p0_0: spi1_miso_p0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ uart1_tx_p0_0: uart1_tx_p0_0 { + pinmux = ; + }; + + /omit-if-no-ref/ swdclk_p0_1: swdclk_p0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ spi1_mosi_p0_1: spi1_mosi_p0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ uart1_rx_p0_1: uart1_rx_p0_1 { + pinmux = ; + }; + + /omit-if-no-ref/ i2c1_scl_p0_2: i2c1_scl_p0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ spi1_sck_p0_2: spi1_sck_p0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ cal32k_p0_2: cal32k_p0_2 { + pinmux = ; + }; + + /omit-if-no-ref/ i2c1_sda_p0_3: i2c1_sda_p0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ spi1_ss0_p0_3: spi1_ss0_p0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ tmr0_p0_3: tmr0_p0_3 { + pinmux = ; + }; + + /omit-if-no-ref/ spi0_miso_p0_4: spi0_miso_p0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ uart0_tx_p0_4: uart0_tx_p0_4 { + pinmux = ; + }; + + /omit-if-no-ref/ spi0_mosi_p0_5: spi0_mosi_p0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ uart0_rx_p0_5: uart0_rx_p0_5 { + pinmux = ; + }; + + /omit-if-no-ref/ spi0_sck_p0_6: spi0_sck_p0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ uart0_cts_p0_6: uart0_cts_p0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ uart1_tx_p0_6: uart1_tx_p0_6 { + pinmux = ; + }; + + /omit-if-no-ref/ spi0_ss0_p0_7: spi0_ss0_p0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ uart0_rts_p0_7: uart0_rts_p0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ uart1_rx_p0_7: uart1_rx_p0_7 { + pinmux = ; + }; + + /omit-if-no-ref/ i2c0_scl_p0_8: i2c0_scl_p0_8 { + pinmux = ; + }; + + /omit-if-no-ref/ swdio_p0_8: swdio_p0_8 { + pinmux = ; + }; + + /omit-if-no-ref/ i2c0_sda_p0_9: i2c0_sda_p0_9 { + pinmux = ; + }; + + /omit-if-no-ref/ swdclk_p0_9: swdclk_p0_9 { + pinmux = ; + }; + + /omit-if-no-ref/ spi1_miso_p0_10: spi1_miso_p0_10 { + pinmux = ; + }; + + /omit-if-no-ref/ uart1_tx_p0_10: uart1_tx_p0_10 { + pinmux = ; + }; + + /omit-if-no-ref/ spi1_mosi_p0_11: spi1_mosi_p0_11 { + pinmux = ; + }; + + /omit-if-no-ref/ uart1_rx_p0_11: uart1_rx_p0_11 { + pinmux = ; + }; + + /omit-if-no-ref/ spi1_sck_p0_12: spi1_sck_p0_12 { + pinmux = ; + }; + + /omit-if-no-ref/ uart1_cts_p0_12: uart1_cts_p0_12 { + pinmux = ; + }; + + /omit-if-no-ref/ spi1_ss0_p0_13: spi1_ss0_p0_13 { + pinmux = ; + }; + + /omit-if-no-ref/ uart1_rts_p0_13: uart1_rts_p0_13 { + pinmux = ; + }; + }; + }; +}; diff --git a/dts/arm/adi/max32/max32660.dtsi b/dts/arm/adi/max32/max32660.dtsi new file mode 100644 index 000000000000..b93b451ffd88 --- /dev/null +++ b/dts/arm/adi/max32/max32660.dtsi @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&clk_ipo { + clock-frequency = ; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(16)>; +}; + +/delete-node/ &clk_iso; +/delete-node/ &clk_ibro; +/delete-node/ &clk_erfo; +/delete-node/ &adc; +/delete-node/ &gpio1; +/delete-node/ &i2c2; +/delete-node/ &uart2; +/delete-node/ &timer3; +/delete-node/ &trng; +/delete-node/ &flash0; + +&flc0 { + flash0: flash@0{ + compatible = "soc-nv-flash"; + reg = <0x00000000 DT_SIZE_K(256)>; + write-block-size = <16>; + erase-block-size = <8192>; + }; +}; + +/* MAX32660 extra peripherals. */ +/ { + chosen { + /delete-property/ zephyr,entropy; + }; + + soc { + sram1: memory@20004000 { + compatible = "mmio-sram"; + reg = <0x20004000 DT_SIZE_K(16)>; + }; + + sram2: memory@20008000 { + compatible = "mmio-sram"; + reg = <0x20008000 DT_SIZE_K(32)>; + }; + + sram3: memory@20010000 { + compatible = "mmio-sram"; + reg = <0x20010000 DT_SIZE_K(32)>; + }; + + dma0: dma@40028000 { + compatible = "adi,max32-dma"; + reg = <0x40028000 0x1000>; + clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>; + interrupts = <28 0>, <29 0>, <30 0>, <31 0>; + dma-channels = <4>; + status = "disabled"; + #dma-cells = <2>; + }; + + spi0: spi@40046000 { + compatible = "adi,max32-spi"; + reg = <0x40046000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcr ADI_MAX32_CLOCK_BUS0 6>; + interrupts = <16 0>; + status = "disabled"; + }; + + spi1: spi@40019000 { + compatible = "adi,max32-spi"; + reg = <0x40019000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcr ADI_MAX32_CLOCK_BUS0 7>; + interrupts = <17 0>; + status = "disabled"; + }; + }; +}; diff --git a/include/zephyr/drivers/clock_control/adi_max32_clock_control.h b/include/zephyr/drivers/clock_control/adi_max32_clock_control.h index cd889d370b25..0f1e7b128823 100644 --- a/include/zephyr/drivers/clock_control/adi_max32_clock_control.h +++ b/include/zephyr/drivers/clock_control/adi_max32_clock_control.h @@ -41,7 +41,7 @@ struct max32_perclk { #define ADI_MAX32_CLK_IPO_FREQ DT_PROP(DT_NODELABEL(clk_ipo), clock_frequency) #define ADI_MAX32_CLK_ERFO_FREQ DT_PROP_OR(DT_NODELABEL(clk_erfo), clock_frequency, 0) -#define ADI_MAX32_CLK_IBRO_FREQ DT_PROP(DT_NODELABEL(clk_ibro), clock_frequency) +#define ADI_MAX32_CLK_IBRO_FREQ DT_PROP_OR(DT_NODELABEL(clk_ibro), clock_frequency, 0) #define ADI_MAX32_CLK_ISO_FREQ DT_PROP_OR(DT_NODELABEL(clk_iso), clock_frequency, 0) #define ADI_MAX32_CLK_INRO_FREQ DT_PROP(DT_NODELABEL(clk_inro), clock_frequency) #define ADI_MAX32_CLK_ERTCO_FREQ DT_PROP(DT_NODELABEL(clk_ertco), clock_frequency) diff --git a/include/zephyr/dt-bindings/dma/max32660_dma.h b/include/zephyr/dt-bindings/dma/max32660_dma.h new file mode 100644 index 000000000000..e52805e1ab64 --- /dev/null +++ b/include/zephyr/dt-bindings/dma/max32660_dma.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32660_DMA_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32660_DMA_H_ + +#define MAX32_DMA_SLOT_MEMTOMEM 0x00U +#define MAX32_DMA_SLOT_SPI0_RX 0x01U +#define MAX32_DMA_SLOT_SPI1_RX 0x02U +#define MAX32_DMA_SLOT_UART0_RX 0x04U +#define MAX32_DMA_SLOT_UART1_RX 0x05U +#define MAX32_DMA_SLOT_I2C0_RX 0x07U +#define MAX32_DMA_SLOT_I2C1_RX 0x08U +#define MAX32_DMA_SLOT_SPI0_TX 0x21U +#define MAX32_DMA_SLOT_SPI1_TX 0x22U +#define MAX32_DMA_SLOT_UART0_TX 0x24U +#define MAX32_DMA_SLOT_UART1_TX 0x25U +#define MAX32_DMA_SLOT_I2C0_TX 0x27U +#define MAX32_DMA_SLOT_I2C1_TX 0x28U + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32660_DMA_H_ */ diff --git a/soc/adi/max32/Kconfig.defconfig.max32660 b/soc/adi/max32/Kconfig.defconfig.max32660 new file mode 100644 index 000000000000..29848d44d1dc --- /dev/null +++ b/soc/adi/max32/Kconfig.defconfig.max32660 @@ -0,0 +1,14 @@ +# Analog Devices MAX32660 MCU + +# Copyright (c) 2025 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MAX32660 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/clocks/clk_ipo,clock-frequency) + +config NUM_IRQS + default 55 + +endif # SOC_MAX32660 diff --git a/soc/adi/max32/Kconfig.soc b/soc/adi/max32/Kconfig.soc index 700a00c3d871..e0be0041b4b6 100644 --- a/soc/adi/max32/Kconfig.soc +++ b/soc/adi/max32/Kconfig.soc @@ -25,6 +25,10 @@ config SOC_MAX32655_M4 select SOC_MAX32655 select SOC_FAMILY_MAX32_M4 +config SOC_MAX32660 + bool + select SOC_FAMILY_MAX32_M4 + config SOC_MAX32662 bool select SOC_FAMILY_MAX32_M4 @@ -84,6 +88,7 @@ config SOC_MAX78002_M4 config SOC default "max32650" if SOC_MAX32650 default "max32655" if SOC_MAX32655 + default "max32660" if SOC_MAX32660 default "max32662" if SOC_MAX32662 default "max32666" if SOC_MAX32666 default "max32670" if SOC_MAX32670 diff --git a/soc/adi/max32/soc.yml b/soc/adi/max32/soc.yml index b08b6e53102e..3bf7288d120d 100644 --- a/soc/adi/max32/soc.yml +++ b/soc/adi/max32/soc.yml @@ -8,6 +8,7 @@ family: - name: max32655 cpuclusters: - name: m4 + - name: max32660 - name: max32662 - name: max32666 cpuclusters: diff --git a/west.yml b/west.yml index 86e16f29fce2..65d565d2ae58 100644 --- a/west.yml +++ b/west.yml @@ -142,7 +142,7 @@ manifest: groups: - fs - name: hal_adi - revision: 13a3f2d44c27416846cde2fe9f23b638c7ad446d + revision: 633fcecf3717aaa22079cf6121627a879f24df51 path: modules/hal/adi groups: - hal