xtensa: move SoC specific out of arch/ and into soc/
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dcpleung
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Removes some unused macros. Signed-off-by: Daniel Leung <[email protected]>
Due to CONFIG_DCACHE_LINE_SIZE=64, the stack is always aligned on 64 bytes. With data cache line size and the default of CONFIG_STACK_POINTER_RANDOM=64 in test, there is not much randomness as any added offset (<= 64) would be rounded up to 64 bytes due to stack alignment. For the added offset to stack pointer to actually mean something, CONFIG_STACK_POINTER_RANDOM has to be larger. Signed-off-by: Daniel Leung <[email protected]>
The newlib that comes with the Xtensa toolchain is very old, and is not thread-safe _at all_. So the newlib tests would fail sometimes but pass in the next run. So skip the newlib tests for intel_adsp platforms. Signed-off-by: Daniel Leung <[email protected]>
Moves the HiFi related kconfigs to their respective SoC kconfigs as it is specific to the SoC... and this requires creating new kconfigs for each SoC series. Signed-off-by: Daniel Leung <[email protected]>
Adds kconfig CONFIG_XTENSA_MMU_USE_DEFAULT_MAPPINGS for arch code to initialize the page tables with a few default mappings covering text, data, BSS and RODATA. Disabling this allows the SoC to customize and fine-tune the mappings if needed. Signed-off-by: Daniel Leung <[email protected]>
This adds the arch default MMU mappings into the SoC mapping array. This is in preparation of not forcibly doing double mapping in architecture code as this type of double mapping should be specified for individual regions. This allows the SoC layer to fine tune the mappings as not anything needs to be double-mapped. Signed-off-by: Daniel Leung <[email protected]>
Rework the SoC MMU mappings in preparation for removal of double mapping code in Xtensa architecture code. This will let the SoC layer and application to fine tune memory mappings instead of having double mapping forcibly applied everywhere. The modified mapping array mimics what the double mapping would have done simply to have the same behavior. Future optimizations can be done to remove unnecessary mappings. Signed-off-by: Daniel Leung <[email protected]>
This removes CONFIG_XTENSA_MMU_DOUBLE_MAP and its associated code. The double mapping of a page into both cached and uncached memory regions should be done in SoC and application, as it gives finer control on what actually is being mapped. For example, if a page only needs to mapped in cached region, there is no need to map it in the uncached region. This may save the need to allocate a L2 page table for it, and saves some memory. Signed-off-by: Daniel Leung <[email protected]>
This is no longer needed for simulator to start other CPUs. So remove it. Signed-off-by: Daniel Leung <[email protected]>
CONFIG_ARCH_HAS_USERSPACE should be in arch layer as MMU and MPU support both in the arch layer. Signed-off-by: Daniel Leung <[email protected]>
The Zephyr linker script usually puts something before z_mapped_start (where .text is), for example, vecbase vectors. So we need to reserve those space or else k_mem_map() would be mapping those which may result in faults. To avoid mapping there, CONFIG_ARCH_HAS_RESERVED_PAGE_FRAMES needs to be used. Since it is common when MMU is enabled, we should enable it by default using imply. All current Xtensa MMU SoCs all have this selected anyway. Using 'imply' instead of 'select' is to allow it to be disabled if so desired. Signed-off-by: Daniel Leung <[email protected]>
This moves the ace-link.ld into include/linker to indicate it is to be included by the main linker script. Also rename it to ace-link-mirrored.ld to indicate that it is for the mirrored cache configuration. Signed-off-by: Daniel Leung <[email protected]>
This adds a kconfig to indicate a memory mapping where physical memory regions are both mirrored and mapped in different addresses. Accessing one set of addresses is via CPU cache while the other is directed to memory. Signed-off-by: Daniel Leung <[email protected]>
The macro ARCH_XTENSA_SET_RPO_TLB is only used for Intel Audio DSP. The specific memory mapping requiring this is SoC specific feature and not a feature on Xtensa in general. It should not be declared in the architecture layer. So move it. Signed-off-by: Daniel Leung <[email protected]>
arch_mem_coherent() is cache related so it is better to move it under cache subsys. It is renamed to sys_cache_is_mem_coherent() to reflect this change. The only user of arch_mem_coherent() is Xtensa. However, it is not an architecture feature. That's why it is moved to the cache subsys. Signed-off-by: Daniel Leung <[email protected]>
This allows SoC to define their custom cache related functions and are used by sys_cache_*() functions. Signed-off-by: Daniel Leung <[email protected]>
Make sure code using these kconfigs are only compiled if they are defined. They will be removed later. But for now, we need these #ifdef to avoid breaking the build when we move these caching functions to SoC layer. Signed-off-by: Daniel Leung <[email protected]>
This re-implements the CONFIG_XTENSA_RPO_CACHE and its cached and uncached region support in the SoC layer. This is in preparation for removing RPO cache in the architecture layer as this is a SoC feature and not an architecture feature. Signed-off-by: Daniel Leung <[email protected]>
This removes the following kconfigs: () CONFIG_XTENSA_RPO_CACHE () CONFIG_XTENSA_CACHED_REGION () CONFIG_XTENSA_UNCACHED_REGION The associated feature is actually SoC specific and not general architecture feature. Since the only user of these have its own implementation, we can now safely remove these. Signed-off-by: Daniel Leung <[email protected]>
Use CONFIG_CACHE_HAS_MIRRORED_MEMORY_REGIONS instead. The new kconfig reflects more correctly on what is going on in hardware. Also, this is not enabled by default if CPU cache is not coherent. CPU cache can be incoherent and yet there are no mirrored memory regions. Those relying on this deprecated default behavior has their config adding CONFIG_CACHE_HAS_MIRRORED_MEMORY_REGIONS separately. Signed-off-by: Daniel Leung <[email protected]>
This adds a spinlock to guard page table counter updates. For some reasons, without this, xt-clang generated code would result in incorrect counter update possibly due to memory access ordering (though GCC generated code works fine without the spin lock). Signed-off-by: Daniel Leung <[email protected]>
During L2 page table duplication, there are cases where we should copy the table over instead of restoring the PTEs. Add the ability to copy the table over. Signed-off-by: Daniel Leung <[email protected]>
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If newlib for this platform is so bad, shouldn't we keep it from being used by applications?
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It is possible that newer toolchains from Cadence have already sorted out the newlib issues, so I don't want to simply disable usage of newlib. It would need to be a choice by the application developers. I don't have access to newer toolchains at this point so I cannot test.
Besides, the default is picolibc. So if the developers really need to use newlib, they will have to explicitly enable it and test.
aescolar
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| * ``CONFIG_ARCH_HAS_COHERENCE`` to :kconfig:option:`CONFIG_CACHE_CAN_SAY_MEM_COHERENCE` as | ||
| the feature is cache related so move it under cache. |
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Minor: It would be nice to phrase it either as what action a user needs to do, or what has changed in a way it is clearly implied what to change.
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| * ``CONFIG_ARCH_HAS_COHERENCE`` to :kconfig:option:`CONFIG_CACHE_CAN_SAY_MEM_COHERENCE` as | |
| the feature is cache related so move it under cache. | |
| * ``CONFIG_ARCH_HAS_COHERENCE`` was renamed :kconfig:option:`CONFIG_CACHE_CAN_SAY_MEM_COHERENCE`. |
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This is mostly about moving SoC specific features and stuff out of the architecture layer and into the SoC layer... mixed in some bug fixes.
See individual commits for more details.