Reapply OOB RAS config after a system reboot#174
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Changes:
1. Monitor CPLD register bit "FM_BIOS_POST_CMPLT_R_N" to check the post status
change.
2. Based on the status change reapply the RAS OOB Config which detects the system
reboot.
3. This eliminates the need to restarting the RAS service to force the config after
a system reboot.
Testing
Run system reboot and check if the oobrasconfig is reconfigured using apml
[root@heliosp-2b805-d7-2 aasaitha]# reboot
apml_tool 0 --getrasoobconfig
================================= APML System Management Interface ====================================
-------------------------------------------------------------
| MCA OOB Err Counter | Enabled |
| DRAM CECC OOB CECC Err Counter Mode | 2 |
| DRAM CECC OOB Leak Rate | 0x14 |
| PCIe OOB Error Reporting Enable | Disabled |
| MCA Thresholding Interrupt Enable | Enabled |
| DRAM CECC Thresholding Interrupt Enable | Enabled |
| PCIE Thresholding Interrupt Enable | Disabled |
| MCA Max Interrupt Rate | 0x1 |
| DRAM CECC Max Interrupt Rate | 0x1 |
| PCIe Max Interrupt Rate | 0x0 |
| MCA OOB Error Reporting Enable | Enabled |
-------------------------------------------------------------
========================================== End of APML SMI ============================================
Signed-off-by: aasaitha <aasaitha@amd.com>
Signed-off-by: aasaitha <aasaitha@amd.com>
Signed-off-by: aasaitha <aasaitha@amd.com>
…listeners Signed-off-by: aasaitha <aasaitha@amd.com>
…n syncflood Signed-off-by: aasaitha <aasaitha@amd.com>
Signed-off-by: aasaitha <aasaitha@amd.com>
raja-gade
approved these changes
Jun 17, 2026
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Pull request overview
This PR adds a mechanism to detect host reboot completion and re-apply APML RAS out-of-band (OOB) configuration automatically, avoiding a manual RAS service restart after reboot. It also introduces a “fatal harvest delay” override configuration and extends when/where several RAS config routines are applied.
Changes:
- Add CPLD/I2C polling for a configurable “POST complete” bit and trigger
platformInitialize()on the rising edge. - Add configurable “FatalHarvestDelay” override and apply it during initialization / runtime polling.
- Update OOB config/threshold application paths (including additional PCIe config/threshold calls) and extend RAS config parsing to include DRAM CECC leak rate.
Reviewed changes
Copilot reviewed 3 out of 3 changed files in this pull request and generated 9 comments.
| File | Description |
|---|---|
| src/apml_manager.cpp | Adds CPLD post-complete polling + reboot detection, applies additional config on events, adds fatal harvest delay override, and extends OOB config parsing. |
| include/apml_manager.hpp | Introduces post-complete monitor config/types and new Manager members/methods (polling timer + D-Bus connection). |
| config/ras_config.json | Adds new JSON attributes for post-complete monitoring and fatal harvest delay; changes a PCIe AER threshold default. |
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| #include <fcntl.h> | ||
| #include <linux/i2c-dev.h> | ||
| #include <sys/ioctl.h> | ||
| #include <unistd.h> | ||
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| #include <stdexcept> |
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| if (i2cBus == nullptr || deviceAddr == nullptr || reg == nullptr || | ||
| bit == nullptr || activeLow == nullptr || pollPeriod == nullptr) | ||
| { | ||
| lg2::error("Post-complete monitor config contains invalid values"); | ||
| postCompleteMonitorConfig.enabled = false; | ||
| return; | ||
| } | ||
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| postCompleteMonitorConfig.name = "ras_config"; | ||
| postCompleteMonitorConfig.i2cBus = *i2cBus; | ||
| postCompleteMonitorConfig.i2cAddress = *deviceAddr; | ||
| postCompleteMonitorConfig.registerOffset = *reg; | ||
| postCompleteMonitorConfig.bit = static_cast<uint8_t>(*bit); | ||
| postCompleteMonitorConfig.activeLow = *activeLow; | ||
| postCompleteMonitorConfig.pollPeriodSec = *pollPeriod; |
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| if (PostCompletePollingEvent != nullptr) | ||
| { | ||
| delete PostCompletePollingEvent; | ||
| } |
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| amd::ras::config::Manager::AttributeValue apmlRetry = | ||
| configMgr.getAttribute("ApmlRetries"); | ||
| int64_t* retryCount = std::get_if<int64_t>(&apmlRetry); | ||
| int64_t retryLimit = *retryCount; | ||
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|
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| oob_config->core_mca_err_reporting_en = | ||
| (dataOut >> PCIE_ERR_REPORT_EN & 1); | ||
| oob_config->dram_cecc_oob_ec_mode = |
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| amd::ras::config::Manager::AttributeValue dramCeccOobEcModeVal = | ||
| configMgr.getAttribute("DramCeccOobEcMode"); | ||
| int64_t* dramCeccOobEcMode = | ||
| std::get_if<int64_t>(&dramCeccOobEcModeVal); | ||
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| amd::ras::config::Manager::AttributeValue dramCeccLeakRateVal = | ||
| configMgr.getAttribute("DramCeccLeakRate"); | ||
| int64_t* dramCeccLeakRate = | ||
| std::get_if<int64_t>(&dramCeccLeakRateVal); | ||
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| oob_config.dram_cecc_oob_ec_mode = | ||
| static_cast<uint8_t>(*dramCeccOobEcMode); | ||
| oob_config.dram_cecc_leak_rate = | ||
| static_cast<uint8_t>(*dramCeccLeakRate); | ||
| oob_config.mca_oob_misc0_ec_enable = 1; |
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| oob_status_t Manager::setPcieOobConfig() | ||
| { | ||
| oob_status_t ret = OOB_MAILBOX_CMD_UNKNOWN; | ||
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| amd::ras::config::Manager::AttributeValue PcieAerPolling = | ||
| configMgr.getAttribute("PcieAerPollingEn"); | ||
| bool* PcieAerPollingEn = std::get_if<bool>(&PcieAerPolling); | ||
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| if (*PcieAerPollingEn == true) | ||
| { | ||
| ret = setPcieOobRegisters(); | ||
| } | ||
| return ret; | ||
| return setPcieOobRegisters(); | ||
| } |
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| amd::ras::config::Manager::AttributeValue apmlRetry = | ||
| configMgr.getAttribute("ApmlRetries"); | ||
| int64_t* retryCount = std::get_if<int64_t>(&apmlRetry); | ||
| int64_t retryLimit = *retryCount; | ||
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| { | ||
| "PcieAerThresholdEn": { | ||
| "Description": "If this field is true, error thresholding for PCIE AER errors will be enabled", | ||
| "Value": false | ||
| "Value": true | ||
| } |
Signed-off-by: aasaitha <aasaitha@amd.com>
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Changes:
1. Monitor CPLD register bit "FM_BIOS_POST_CMPLT_R_N" to check the post status change.
2. Based on the status change reapply the RAS OOB Config which detects the system reboot.
3. This eliminates the need to restarting the RAS service to force the config after a system reboot.
Working re-apply config sets for MCA and DRAM after system reboot.txt