Change for consistent spaces across sbsa and bsa (#459)

- When the rule id is printed in next line, there is a diff in the no. of spaces. - Made the spaces consistent between sbsa and bsa for all tests Change-Id: I496243bfe46174a35ffaed3cddf5ef213ea28def Signed-off-by: Sujana M <[email protected]>
ARM-software · May 7, 2024 · 6fe46b1 · 6fe46b1
1 parent 4503ffb
commit 6fe46b1
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Showing 154 changed files with 170 additions and 170 deletions.
diff --git a/test_pool/ete/operating_system/test_ete001.c b/test_pool/ete/operating_system/test_ete001.c
@@ -22,7 +22,7 @@
 
 #define TEST_NUM   (ACS_ETE_TEST_NUM_BASE + 1)
 #define TEST_RULE  "ETE_02"
-#define TEST_DESC  "Check for FEAT_ETE                "
+#define TEST_DESC  "Check for FEAT_ETE                    "
 
 static void payload(void)
 {

diff --git a/test_pool/ete/operating_system/test_ete002.c b/test_pool/ete/operating_system/test_ete002.c
@@ -22,7 +22,7 @@
 
 #define TEST_NUM   (ACS_ETE_TEST_NUM_BASE + 2)
 #define TEST_RULE  "ETE_03"
-#define TEST_DESC  "Check trace unit ETE supports     "
+#define TEST_DESC  "Check trace unit ETE supports         "
 
 static void payload(void)
 {

diff --git a/test_pool/ete/operating_system/test_ete003.c b/test_pool/ete/operating_system/test_ete003.c
@@ -27,7 +27,7 @@
 
 #define TEST_NUM   (ACS_ETE_TEST_NUM_BASE + 3)
 #define TEST_RULE  "ETE_04, ETE_06"
-#define TEST_DESC  "Check ETE Trace Timestamp Source  "
+#define TEST_DESC  "Check ETE Trace Timestamp Source      "
 
 volatile uint64_t buffer_addr;
 volatile uint64_t *start_timestamp;

diff --git a/test_pool/ete/operating_system/test_ete004.c b/test_pool/ete/operating_system/test_ete004.c
@@ -24,7 +24,7 @@
 
 #define TEST_NUM   (ACS_ETE_TEST_NUM_BASE + 4)
 #define TEST_RULE  "ETE_05"
-#define TEST_DESC  "Check Trace Same Timestamp Source "
+#define TEST_DESC  "Check Trace Same Timestamp Source     "
 
 volatile uint64_t trace_buffer_addr;
 

diff --git a/test_pool/ete/operating_system/test_ete005.c b/test_pool/ete/operating_system/test_ete005.c
@@ -22,7 +22,7 @@
 
 #define TEST_NUM   (ACS_ETE_TEST_NUM_BASE + 5)
 #define TEST_RULE  "ETE_07"
-#define TEST_DESC  "Check for FEAT_TRBE               "
+#define TEST_DESC  "Check for FEAT_TRBE                   "
 
 static void payload(void)
 {

diff --git a/test_pool/ete/operating_system/test_ete006.c b/test_pool/ete/operating_system/test_ete006.c
@@ -22,7 +22,7 @@
 
 #define TEST_NUM   (ACS_ETE_TEST_NUM_BASE + 6)
 #define TEST_RULE  "ETE_08"
-#define TEST_DESC  "Check trace buffers flag updates  "
+#define TEST_DESC  "Check trace buffers flag updates      "
 
 static uint32_t primary_pe_flag_updates;
 

diff --git a/test_pool/ete/operating_system/test_ete007.c b/test_pool/ete/operating_system/test_ete007.c
@@ -22,7 +22,7 @@
 
 #define TEST_NUM   (ACS_ETE_TEST_NUM_BASE + 7)
 #define TEST_RULE  "ETE_09"
-#define TEST_DESC  "Check TRBE trace buffers alignment"
+#define TEST_DESC  "Check TRBE trace buffers alignment    "
 
 static uint32_t min_trace_alignment;
 

diff --git a/test_pool/ete/operating_system/test_ete008.c b/test_pool/ete/operating_system/test_ete008.c
@@ -23,7 +23,7 @@
 
 #define TEST_NUM   (ACS_ETE_TEST_NUM_BASE + 8)
 #define TEST_RULE  "ETE_10"
-#define TEST_DESC  "Check GICC TRBE Interrupt field   "
+#define TEST_DESC  "Check GICC TRBE Interrupt field       "
 
 static void payload(void)
 {

diff --git a/test_pool/exerciser/operating_system/test_e001.c b/test_pool/exerciser/operating_system/test_e001.c
@@ -23,7 +23,7 @@
 #include "val/sbsa/include/sbsa_acs_exerciser.h"
 
 #define TEST_NUM   (ACS_EXERCISER_TEST_NUM_BASE + 1)
-#define TEST_DESC  "Enhanced ECAM Memory access check "
+#define TEST_DESC  "Enhanced ECAM Memory access check     "
 #define TEST_RULE  ""
 
 static

diff --git a/test_pool/exerciser/operating_system/test_e002.c b/test_pool/exerciser/operating_system/test_e002.c
@@ -30,7 +30,7 @@
 #include "val/sbsa/include/sbsa_acs_exerciser.h"
 
 #define TEST_NUM   (ACS_EXERCISER_TEST_NUM_BASE + 2)
-#define TEST_DESC  "PCIe Address translation check    "
+#define TEST_DESC  "PCIe Address translation check        "
 #define TEST_RULE  "RE_SMU_2"
 
 #define TEST_DATA_NUM_PAGES  4

diff --git a/test_pool/exerciser/operating_system/test_e003.c b/test_pool/exerciser/operating_system/test_e003.c
@@ -30,7 +30,7 @@
 #include "val/sbsa/include/sbsa_acs_exerciser.h"
 
 #define TEST_NUM   (ACS_EXERCISER_TEST_NUM_BASE + 3)
-#define TEST_DESC  "ATS Functionality Check           "
+#define TEST_DESC  "ATS Functionality Check               "
 #define TEST_RULE  "RE_SMU_2"
 
 #define TEST_DATA_NUM_PAGES  1

diff --git a/test_pool/exerciser/operating_system/test_e004.c b/test_pool/exerciser/operating_system/test_e004.c
@@ -26,7 +26,7 @@
 #include "val/sbsa/include/sbsa_acs_exerciser.h"
 
 #define TEST_NUM   (ACS_EXERCISER_TEST_NUM_BASE + 4)
-#define TEST_DESC  "Arrival order & Gathering Check   "
+#define TEST_DESC  "Arrival order & Gathering Check       "
 #define TEST_RULE  "RE_ORD_1, RE_ORD_2, IE_ORD_1, IE_ORD_2"
 
 /* 0 means read transction, 1 means write transaction */

diff --git a/test_pool/exerciser/operating_system/test_e005.c b/test_pool/exerciser/operating_system/test_e005.c
@@ -27,7 +27,7 @@
 #include "val/sbsa/include/sbsa_acs_exerciser.h"
 
 #define TEST_NUM   (ACS_EXERCISER_TEST_NUM_BASE + 5)
-#define TEST_DESC  "PE 2/4/8B writes to PCIe as 2/4/8B"
+#define TEST_DESC  "PE 2/4/8B writes to PCIe as 2/4/8B    "
 #define TEST_RULE  "S_PCIe_03"
 
 static uint32_t transaction_size = 4;

diff --git a/test_pool/exerciser/operating_system/test_e006.c b/test_pool/exerciser/operating_system/test_e006.c
@@ -29,7 +29,7 @@
 #include "val/sbsa/include/sbsa_acs_exerciser.h"
 
 #define TEST_NUM   (ACS_EXERCISER_TEST_NUM_BASE + 6)
-#define TEST_DESC  "RP's must support AER feature          "
+#define TEST_DESC  "RP's must support AER feature         "
 #define TEST_RULE  "PCI_ER_01, PCI_ER_02, PCI_ER_03, PCI_ER_04"
 
 #define ERR_CORR     0x2

diff --git a/test_pool/exerciser/operating_system/test_e007.c b/test_pool/exerciser/operating_system/test_e007.c
@@ -28,7 +28,7 @@
 #include "val/sbsa/include/sbsa_acs_exerciser.h"
 
 #define TEST_NUM   (ACS_EXERCISER_TEST_NUM_BASE + 7)
-#define TEST_DESC  "RP's must support DPC                  "
+#define TEST_DESC  "RP's must support DPC                 "
 #define TEST_RULE  "PCI_ER_05, PCI_ER_06"
 
 #define ERR_FATAL 1

diff --git a/test_pool/exerciser/operating_system/test_e008.c b/test_pool/exerciser/operating_system/test_e008.c
@@ -27,7 +27,7 @@
 #include "val/sbsa/include/sbsa_acs_pcie.h"
 
 #define TEST_NUM   (ACS_EXERCISER_TEST_NUM_BASE + 8)
-#define TEST_DESC  "Check 2/4/8 Bytes targeted writes"
+#define TEST_DESC  "Check 2/4/8 Bytes targeted writes     "
 #define TEST_RULE  "S_PCIe_04"
 
 

diff --git a/test_pool/exerciser/operating_system/test_e009.c b/test_pool/exerciser/operating_system/test_e009.c
@@ -27,7 +27,7 @@
 #include "val/sbsa/include/sbsa_acs_exerciser.h"
 
 #define TEST_NUM   (ACS_EXERCISER_TEST_NUM_BASE + 9)
-#define TEST_DESC  "Check Relaxed Ordering of writes  "
+#define TEST_DESC  "Check Relaxed Ordering of writes      "
 #define TEST_RULE  "S_PCIe_07, S_PCIe_08"
 
 #define DMA_BUFF_LEN 0x8

diff --git a/test_pool/exerciser/operating_system/test_e010.c b/test_pool/exerciser/operating_system/test_e010.c
@@ -29,7 +29,7 @@
 #include "val/sbsa/include/sbsa_acs_exerciser.h"
 
 #define TEST_NUM   (ACS_EXERCISER_TEST_NUM_BASE + 10)
-#define TEST_DESC  "DPC trig when RP-PIO unimplemented"
+#define TEST_DESC  "DPC trig when RP-PIO unimplemented    "
 #define TEST_RULE  "PCI_ER_10"
 
 #define ERR_UNCORR   0x3

diff --git a/test_pool/exerciser/operating_system/test_e011.c b/test_pool/exerciser/operating_system/test_e011.c
@@ -26,7 +26,7 @@
 
 #define TEST_NUM   (ACS_EXERCISER_TEST_NUM_BASE + 11)
 #define TEST_RULE  "PCI_ER_08"
-#define TEST_DESC  "RAS ERR record for poisoned data  "
+#define TEST_DESC  "RAS ERR record for poisoned data      "
 
 static
 void

diff --git a/test_pool/exerciser/operating_system/test_e012.c b/test_pool/exerciser/operating_system/test_e012.c
@@ -26,7 +26,7 @@
 #include "val/sbsa/include/sbsa_acs_exerciser.h"
 
 #define TEST_NUM   (ACS_EXERCISER_TEST_NUM_BASE + 12)
-#define TEST_DESC  "RAS ERR record for external abort "
+#define TEST_DESC  "RAS ERR record for external abort     "
 #define TEST_RULE  "PCI_ER_07"
 
 static void *branch_to_test;

diff --git a/test_pool/gic/operating_system/test_g001.c b/test_pool/gic/operating_system/test_g001.c
@@ -22,7 +22,7 @@
 
 #define TEST_NUM   (ACS_GIC_TEST_NUM_BASE + 1)
 #define TEST_RULE  "S_L3GI_01"
-#define TEST_DESC  "Check GIC version                 "
+#define TEST_DESC  "Check GIC version                     "
 
 static
 void

diff --git a/test_pool/gic/operating_system/test_g002.c b/test_pool/gic/operating_system/test_g002.c
@@ -23,7 +23,7 @@
 
 #define TEST_NUM   (ACS_GIC_TEST_NUM_BASE + 2)
 #define TEST_RULE  "S_L5PP_01"
-#define TEST_DESC  "Check Reserved PPI Assignments    "
+#define TEST_DESC  "Check Reserved PPI Assignments        "
 
 /* PPI IDs 1056-1071 and 1088-1103 are reserved for future SBSA usage */
 #define IS_PPI_RESERVED(id) ((id > 1055 && id < 1072) || (id > 1087 && id < 1104))

diff --git a/test_pool/memory_map/operating_system/test_m001.c b/test_pool/memory_map/operating_system/test_m001.c
@@ -23,7 +23,7 @@
 
 #define TEST_NUM (ACS_MEMORY_MAP_TEST_NUM_BASE + 1)
 #define TEST_RULE "S_L3MM_01, S_L3MM_02"
-#define TEST_DESC "Check peripherals addr 64Kb apart "
+#define TEST_DESC "Check peripherals addr 64Kb apart     "
 
 static void payload(void)
 {

diff --git a/test_pool/mpam/operating_system/test_mpam001.c b/test_pool/mpam/operating_system/test_mpam001.c
@@ -23,9 +23,9 @@
 #include "val/sbsa/include/sbsa_acs_mpam.h"
 
 
-#define TEST_NUM (ACS_MPAM_TEST_NUM_BASE + 1)
-#define TEST_RULE "S_L7MP_01, S_L7MP_02"
-#define TEST_DESC "Check for MPAM extension          "
+#define TEST_NUM   (ACS_MPAM_TEST_NUM_BASE + 1)
+#define TEST_RULE  "S_L7MP_01, S_L7MP_02"
+#define TEST_DESC  "Check for MPAM extension              "
 
 static void payload(void)
 {

diff --git a/test_pool/mpam/operating_system/test_mpam002.c b/test_pool/mpam/operating_system/test_mpam002.c
@@ -23,9 +23,9 @@
 #include "val/sbsa/include/sbsa_acs_mpam.h"
 
 
-#define TEST_NUM (ACS_MPAM_TEST_NUM_BASE + 2)
-#define TEST_RULE "S_L7MP_03, S_L7MP_04"
-#define TEST_DESC "Check for MPAM LLC CSU            "
+#define TEST_NUM   (ACS_MPAM_TEST_NUM_BASE + 2)
+#define TEST_RULE  "S_L7MP_03, S_L7MP_04"
+#define TEST_DESC  "Check for MPAM LLC CSU                "
 
 static void payload(void)
 {

diff --git a/test_pool/mpam/operating_system/test_mpam003.c b/test_pool/mpam/operating_system/test_mpam003.c
@@ -24,9 +24,9 @@
 #include "val/sbsa/include/sbsa_acs_mpam.h"
 
 
-#define TEST_NUM  (ACS_MPAM_TEST_NUM_BASE + 3)
-#define TEST_RULE "S_L7MP_05, S_L7MP_06"
-#define TEST_DESC "Check for MPAM MBWUs Monitor func "
+#define TEST_NUM   (ACS_MPAM_TEST_NUM_BASE + 3)
+#define TEST_RULE  "S_L7MP_05, S_L7MP_06"
+#define TEST_DESC  "Check for MPAM MBWUs Monitor func     "
 
 #define BUFFER_SIZE 65536 /* 64 Kilobytes*/
 

diff --git a/test_pool/mpam/operating_system/test_mpam004.c b/test_pool/mpam/operating_system/test_mpam004.c
@@ -24,9 +24,9 @@
 #include "val/sbsa/include/sbsa_acs_mpam.h"
 
 
-#define TEST_NUM  (ACS_MPAM_TEST_NUM_BASE + 4)
-#define TEST_RULE "S_L7MP_07"
-#define TEST_DESC "Check for MBWU counter size       "
+#define TEST_NUM   (ACS_MPAM_TEST_NUM_BASE + 4)
+#define TEST_RULE  "S_L7MP_07"
+#define TEST_DESC  "Check for MBWU counter size           "
 
 #define MBWU_COUNTER_44BIT 0
 #define MAX_44BIT_COUNTER_BW 1677722 /* this is in MB (1.6 TB) */

diff --git a/test_pool/mpam/operating_system/test_mpam005.c b/test_pool/mpam/operating_system/test_mpam005.c
@@ -22,9 +22,9 @@
 #include "val/sbsa/include/sbsa_acs_mpam.h"
 #include "val/common/include/acs_peripherals.h"
 
-#define TEST_NUM (ACS_MPAM_TEST_NUM_BASE + 5)
-#define TEST_RULE "S_L7MP_08"
-#define TEST_DESC "Check for MPAM MSC address overlap"
+#define TEST_NUM   (ACS_MPAM_TEST_NUM_BASE + 5)
+#define TEST_RULE  "S_L7MP_08"
+#define TEST_DESC  "Check for MPAM MSC address overlap    "
 
 static void payload(void)
 {

diff --git a/test_pool/mpam/operating_system/test_mpam006.c b/test_pool/mpam/operating_system/test_mpam006.c
@@ -23,9 +23,9 @@
 #include "val/sbsa/include/sbsa_acs_mpam.h"
 #include "val/sbsa/include/sbsa_acs_memory.h"
 
-#define TEST_NUM (ACS_MPAM_TEST_NUM_BASE + 6)
-#define TEST_RULE "S_L7MP_03"
-#define TEST_DESC "Check PMG storage by CPOR nodes   "
+#define TEST_NUM   (ACS_MPAM_TEST_NUM_BASE + 6)
+#define TEST_RULE  "S_L7MP_03"
+#define TEST_DESC  "Check PMG storage by CPOR nodes       "
 
 #define PARTITION_PERCENTAGE 75
 #define CACHE_PERCENTAGE 50

diff --git a/test_pool/nist_sts/test_n001.c b/test_pool/nist_sts/test_n001.c
@@ -26,7 +26,7 @@
 
 #define TEST_NUM   (ACS_NIST_TEST_NUM_BASE + 1)
 #define TEST_RULE "S_L7ENT_1"
-#define TEST_DESC  "NIST Statistical Test Suite       "
+#define TEST_DESC  "NIST Statistical Test Suite           "
 
 #define BUFFER_SIZE     1000
 #define RND_FILE_SIZE   36428

diff --git a/test_pool/pcie/operating_system/test_p001.c b/test_pool/pcie/operating_system/test_p001.c
@@ -19,7 +19,7 @@
 #include "val/sbsa/include/sbsa_acs_pcie.h"
 
 #define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 1)
-#define TEST_DESC  "Check ECAM Presence               "
+#define TEST_DESC  "Check ECAM Presence                   "
 #define TEST_RULE  "PCI_IN_01"
 
 static

diff --git a/test_pool/pcie/operating_system/test_p003.c b/test_pool/pcie/operating_system/test_p003.c
@@ -23,7 +23,7 @@
 #include "val/sbsa/include/sbsa_acs_pe.h"
 
 #define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 3)
-#define TEST_DESC  "Check ECAM Memory accessibility   "
+#define TEST_DESC  "Check ECAM Memory accessibility       "
 #define TEST_RULE  "PCI_IN_02"
 
 static void *branch_to_test;

diff --git a/test_pool/pcie/operating_system/test_p005.c b/test_pool/pcie/operating_system/test_p005.c
@@ -22,7 +22,7 @@
 
 /* SBSA-checklist 63 & 64 */
 #define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 5)
-#define TEST_DESC  "PCIe Unaligned access, Norm mem   "
+#define TEST_DESC  "PCIe Unaligned access, Norm mem       "
 #define TEST_RULE  "PCI_MM_01, PCI_MM_02, PCI_MM_03, RE_BAR_2, IE_BAR_2"
 
 #define DATA 0xC0DECAFE

diff --git a/test_pool/pcie/operating_system/test_p009.c b/test_pool/pcie/operating_system/test_p009.c
@@ -21,7 +21,7 @@
 #include "val/sbsa/include/sbsa_acs_pcie.h"
 
 #define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 9)
-#define TEST_DESC  "Check all MSI(X) vectors are LPIs "
+#define TEST_DESC  "Check all MSI(X) vectors are LPIs     "
 #define TEST_RULE  "S_L3GI_02"
 
 #define LPI_BASE 8192

diff --git a/test_pool/pcie/operating_system/test_p016.c b/test_pool/pcie/operating_system/test_p016.c
@@ -20,7 +20,7 @@
 #include "val/sbsa/include/sbsa_acs_pcie.h"
 
 #define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 16)
-#define TEST_DESC  "NP type-1 pcie only support 32-bit"
+#define TEST_DESC  "NP type-1 pcie only support 32-bit    "
 #define TEST_RULE  "PCI_MM_04"
 
 #define BAR0    0x10

diff --git a/test_pool/pcie/operating_system/test_p020.c b/test_pool/pcie/operating_system/test_p020.c
@@ -21,7 +21,7 @@
 #include "test_p020_data.h"
 
 #define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 20)
-#define TEST_DESC  "Check Type 0/1 common config rules"
+#define TEST_DESC  "Check Type 0/1 common config rules    "
 #define TEST_RULE  "RE_REG_1, IE_REG_1, IE_REG_3"
 
 static

diff --git a/test_pool/pcie/operating_system/test_p021.c b/test_pool/pcie/operating_system/test_p021.c
@@ -21,7 +21,7 @@
 #include "test_p021_data.h"
 
 #define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 21)
-#define TEST_DESC  "Check Type 0 config header rules  "
+#define TEST_DESC  "Check Type 0 config header rules      "
 #define TEST_RULE  "RE_REG_1, IE_REG_1"
 
 static

diff --git a/test_pool/pcie/operating_system/test_p022.c b/test_pool/pcie/operating_system/test_p022.c
@@ -21,7 +21,7 @@
 #include "test_p022_data.h"
 
 #define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 22)
-#define TEST_DESC  "Check Type 1 config header rules  "
+#define TEST_DESC  "Check Type 1 config header rules      "
 #define TEST_RULE  "IE_REG_3"
 
 static

diff --git a/test_pool/pcie/operating_system/test_p023.c b/test_pool/pcie/operating_system/test_p023.c
@@ -21,7 +21,7 @@
 #include "test_p023_data.h"
 
 #define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 23)
-#define TEST_DESC  "Check PCIe capability rules       "
+#define TEST_DESC  "Check PCIe capability rules           "
 #define TEST_RULE  "IE_REG_4"
 
 static

diff --git a/test_pool/pcie/operating_system/test_p024.c b/test_pool/pcie/operating_system/test_p024.c
@@ -21,7 +21,7 @@
 #include "test_p024_data.h"
 
 #define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 24)
-#define TEST_DESC  "Check Device capabilities reg rule"
+#define TEST_DESC  "Check Device capabilities reg rule    "
 #define TEST_RULE  "RE_REG_3, RE_REC_1, IE_REG_2, IE_REG_4"
 
 static

diff --git a/test_pool/pcie/operating_system/test_p025.c b/test_pool/pcie/operating_system/test_p025.c
@@ -21,7 +21,7 @@
 #include "test_p025_data.h"
 
 #define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 25)
-#define TEST_DESC  "Check Device Control register rule"
+#define TEST_DESC  "Check Device Control register rule    "
 #define TEST_RULE  "RE_REG_3, RE_REC_1, IE_REG_2, IE_REG_4"
 
 static