Skip to content
View AbdurRahman020's full-sized avatar
🎯
Focusing
🎯
Focusing

Block or report AbdurRahman020

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
AbdurRahman020/README.md

Abdur Rahman

Introduction

I am an Electrical Engineering student aspiring to specialize in FPGA design and verification. I'm actively learning SystemVerilog and exploring the intersection of hardware design and AI acceleration. My goal is to build a career in FPGA engineering, focusing on AI hardware implementation and verification.

Skills & Tools

  • Hardware Design & Verification: SystemVerilog, FPGA
  • Programming Languages: Python, C, C++, MATLAB
  • Development Tools: Git, Linux/Ubuntu, Vim
  • Problem Solving: LeetCode (occasional practice)

Contact

Stats

Stats

Pinned Loading

  1. digital-design-journey digital-design-journey Public

    Learning digital design through SystemVerilog — RTL, FSMs, FPGA, and eventually RISC-V

    SystemVerilog

  2. data-structure-and-algorithm data-structure-and-algorithm Public

    contain codes from university course

    Python

  3. ee-labs-and-simulations ee-labs-and-simulations Public

    LTSpice and MATLAB simulations from university coursework

    MATLAB