File tree Expand file tree Collapse file tree 3 files changed +8
-5
lines changed
mfb_tools/debug/frame_recorder Expand file tree Collapse file tree 3 files changed +8
-5
lines changed Original file line number Diff line number Diff line change @@ -124,7 +124,7 @@ architecture FULL of TCAM2 is
124
124
signal input_wr_addr_reg : std_logic_vector (WRITE_ADDR'range );
125
125
126
126
-- Input registers augmented
127
- signal input_m_data_reg_aug : std_logic_vector (COLUMNS* CELL_WIDTH- 1 downto 0 );
127
+ signal input_m_data_reg_aug : std_logic_vector (COLUMNS* CELL_WIDTH- 1 downto 0 ) := ( others => '0' ) ;
128
128
signal input_wr_data_reg_aug : std_logic_vector (COLUMNS* CELL_WIDTH- 1 downto 0 ) := (others => '0' );
129
129
signal input_wr_mask_reg_aug : std_logic_vector (COLUMNS* CELL_WIDTH- 1 downto 0 ) := (others => '0' );
130
130
@@ -500,7 +500,7 @@ begin
500
500
end process ;
501
501
502
502
-- match data register padding
503
- input_m_data_reg_aug <= (input_m_data_reg'range => input_m_data_reg, others => '0' ) ;
503
+ input_m_data_reg_aug(input_m_data_reg'range ) <= input_m_data_reg;
504
504
-- match data register array
505
505
input_m_data_reg_aug_arr <= slv_array_deser(input_m_data_reg_aug,COLUMNS);
506
506
Original file line number Diff line number Diff line change @@ -289,7 +289,8 @@ begin
289
289
interval_len <= resize (unsigned (MI_DWR), INTERVAL_LEN_WIDTH);
290
290
end if ;
291
291
if (MI_RESET = '1' ) then
292
- interval_len <= (INTERVAL_LEN_WIDTH/ 2 => '1' , others => '0' );
292
+ interval_len <= (others => '0' );
293
+ interval_len(INTERVAL_LEN_WIDTH/ 2 ) <= '1' ;
293
294
end if ;
294
295
end if ;
295
296
end process ;
Original file line number Diff line number Diff line change @@ -105,8 +105,10 @@ begin
105
105
s_drd_premuxed(31 downto 0 ) <= s_sreg;
106
106
s_drd_premuxed(63 downto 32 ) <= s_creg;
107
107
s_drd_premuxed(95 downto 64 ) <= s_fifo2mi_flow_ctrl;
108
- s_drd_premuxed(127 downto 96 ) <= (96 + SOF_POS_WIDTH- 1 downto 96 => s_fifo_out.sof_pos, others => '0' );
109
- s_drd_premuxed(159 downto 128 ) <= (128 + EOF_POS_WIDTH- 1 downto 128 => s_fifo_out.eof_pos, others => '0' );
108
+ s_drd_premuxed(127 downto 96 + SOF_POS_WIDTH) <= (others => '0' );
109
+ s_drd_premuxed(96 + SOF_POS_WIDTH- 1 downto 96 ) <= s_fifo_out.sof_pos;
110
+ s_drd_premuxed(159 downto 128 + EOF_POS_WIDTH) <= (others => '0' );
111
+ s_drd_premuxed(128 + EOF_POS_WIDTH- 1 downto 128 ) <= s_fifo_out.eof_pos;
110
112
111
113
s_drd_premuxed_g : for i in 0 to MI_DATA_ITEMS- 1 generate
112
114
s_drd_premuxed((i+ 5 + 1 )* 32 - 1 downto (i+ 5 )* 32 ) <= s_fifo_out.data((i+ 1 )* 32 - 1 downto i* 32 );
You can’t perform that action at this time.
0 commit comments