Cyrix 6x86: Correctly initalize ARR3 on reset to avoid some SMM problems

Cacodemon345 · Mar 5, 2025 · c40aa61 · c40aa61
1 parent 5f3641e
commit c40aa61
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/src/cpu/x86.c b/src/cpu/x86.c
@@ -275,6 +275,8 @@ reset_common(int hard)
 
     ccr0 = ccr1 = ccr2 = ccr3 = ccr4 = ccr5 = ccr6 = ccr7 = 0;
     ccr4 = 0x85;
+    cyrix.arr[3].base = 0x30000;
+    cyrix.arr[3].size = 65536;
 
     if (hascache)
         cr0 = 1 << 30;