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feat: add more avx512 instructions
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@gbotrel
gbotrel committed Feb 2, 2025
1 parent 89ff477 commit f4563f8
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Showing 3 changed files with 994 additions and 3 deletions.
207 changes: 207 additions & 0 deletions amd64/instructions.go
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Original file line number Diff line number Diff line change
Expand Up @@ -63,6 +63,56 @@ func (amd64 *Amd64) VMOVSHDUP(r1, r2 interface{}, comment ...string) {
amd64.writeOp(comment, "VMOVSHDUP", r1, r2)
}

// VMOVSHDUPk: Move Packed Single-FP High and Duplicate
func (amd64 *Amd64) VMOVSHDUPk(r1, k, r2 interface{}, comment ...string) {
amd64.writeOp(comment, "VMOVSHDUP", r1, k, r2)
}

// VPCMPUD: Compare Packed Unsigned Doubleword Values.
//
// Forms:
//
// VPCMPUD imm8 m128 xmm k k
// VPCMPUD imm8 m128 xmm k
// VPCMPUD imm8 m256 ymm k k
// VPCMPUD imm8 m256 ymm k
// VPCMPUD imm8 xmm xmm k k
// VPCMPUD imm8 xmm xmm k
// VPCMPUD imm8 ymm ymm k k
// VPCMPUD imm8 ymm ymm k
// VPCMPUD imm8 m512 zmm k k
// VPCMPUD imm8 m512 zmm k
// VPCMPUD imm8 zmm zmm k k
// VPCMPUD imm8 zmm zmm k
func (amd64 *Amd64) VPCMPUD(imm8, r1, r2, k interface{}, comment ...string) {
amd64.writeOp(comment, "VPCMPUD", imm8, r1, r2, k)
}

// VPMADD52HUQ: Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to Quadword Accumulators.
//
// Forms:
//
// VPMADD52HUQ m128 xmm k xmm
// VPMADD52HUQ m128 xmm xmm
// VPMADD52HUQ m256 ymm k ymm
// VPMADD52HUQ m256 ymm ymm
// VPMADD52HUQ xmm xmm k xmm
// VPMADD52HUQ xmm xmm xmm
// VPMADD52HUQ ymm ymm k ymm
// VPMADD52HUQ ymm ymm ymm
// VPMADD52HUQ m512 zmm k zmm
// VPMADD52HUQ m512 zmm zmm
// VPMADD52HUQ zmm zmm k zmm
// VPMADD52HUQ zmm zmm zmm
func (amd64 *Amd64) VPMADD52HUQ(r1, r2, r3 any, comment ...string) {
amd64.writeOp(comment, "VPMADD52HUQ", r1, r2, r3)
}

// VPMADD52LUQ: Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit Products to Quadword Accumulators.
func (amd64 *Amd64) VPMADD52LUQ(r1, r2, r3 any, comment ...string) {
amd64.writeOp(comment, "VPMADD52LUQ", r1, r2, r3)
}

// VPBROADCASTQ: Broadcast Quadword Integer
func (amd64 *Amd64) VPBROADCASTQ(r1, r2 interface{}, comment ...string) {
amd64.writeOp(comment, "VPBROADCASTQ", r1, r2)
Expand All @@ -78,6 +128,11 @@ func (amd64 *Amd64) VPADDD(r1, r2, r3 interface{}, comment ...string) {
amd64.writeOp(comment, "VPADDD", r1, r2, r3)
}

// VPADDDk: Add Packed Doubleword Integers
func (amd64 *Amd64) VPADDDk(r1, r2, k, r3 interface{}, comment ...string) {
amd64.writeOp(comment, "VPADDD", r1, r2, k, r3)
}

// VPSUBD: Subtract Packed Doubleword Integers
func (amd64 *Amd64) VPSUBD(r1, r2, r3 interface{}, comment ...string) {
amd64.writeOp(comment, "VPSUBD", r1, r2, r3)
Expand Down Expand Up @@ -282,6 +337,41 @@ func (amd64 *Amd64) VMOVDQA32(r1, r2 interface{}, comment ...string) {
amd64.writeOp(comment, "VMOVDQA32", r1, r2)
}

// VPSRLD: Shift Packed Doubleword Data Right Logical.
func (amd64 *Amd64) VPSRLD(imm8, r2, r3 interface{}, comment ...string) {
amd64.writeOp(comment, "VPSRLD", imm8, r2, r3)
}

// VPSHUFLW: Shuffle Packed Low Words.
func (amd64 *Amd64) VPSHUFLW(imm8, r1, r2 interface{}, comment ...string) {
amd64.writeOp(comment, "VPSHUFLW", imm8, r1, r2)
}

// VPSHUFHW: Shuffle Packed High Words.
func (amd64 *Amd64) VPSHUFHW(imm8, r1, r2 interface{}, comment ...string) {
amd64.writeOp(comment, "VPSHUFHW", imm8, r1, r2)
}

// VPMOVDW: Down Convert Packed Doubleword Values to Word Values with Truncation.
//
// Forms:
//
// VPMOVDW xmm k m64
// VPMOVDW xmm k xmm
// VPMOVDW xmm m64
// VPMOVDW xmm xmm
// VPMOVDW ymm k m128
// VPMOVDW ymm k xmm
// VPMOVDW ymm m128
// VPMOVDW ymm xmm
// VPMOVDW zmm k m256
// VPMOVDW zmm k ymm
// VPMOVDW zmm m256
// VPMOVDW zmm ymm
func (amd64 *Amd64) VPMOVDW(r1, r2 interface{}, comment ...string) {
amd64.writeOp(comment, "VPMOVDW", r1, r2)
}

// VMOVDQA64 Move Aligned Quadword Values
func (amd64 *Amd64) VMOVDQA64(r1, r2 interface{}, comment ...string) {
amd64.writeOp(comment, "VMOVDQA64", r1, r2)
Expand All @@ -302,6 +392,26 @@ func (amd64 *Amd64) VPMOVZXDQ(r1, r2 interface{}, comment ...string) {
amd64.writeOp(comment, "VPMOVZXDQ", r1, r2)
}

// VPMOVZXWD: Move Packed Word Integers to Doubleword Integers with Zero Extension.
//
// Forms:
//
// VPMOVZXWD m128 ymm
// VPMOVZXWD xmm ymm
// VPMOVZXWD m64 xmm
// VPMOVZXWD xmm xmm
// VPMOVZXWD m128 k ymm
// VPMOVZXWD m64 k xmm
// VPMOVZXWD xmm k xmm
// VPMOVZXWD xmm k ymm
// VPMOVZXWD m256 k zmm
// VPMOVZXWD m256 zmm
// VPMOVZXWD ymm k zmm
// VPMOVZXWD ymm zmm
func (amd64 *Amd64) VPMOVZXWD(r1, r2 VectorRegister, comment ...string) {
amd64.writeOp(comment, "VPMOVZXWD", r1, r2)
}

// VPSHUFD: Shuffle Packed Doublewords.
//
// Forms:
Expand Down Expand Up @@ -342,6 +452,62 @@ func (amd64 *Amd64) VSHUFPD(imm8, r1, r2, r3 interface{}, comment ...string) {
amd64.writeOp(comment, "VSHUFPD", imm8, r1, r2, r3)
}

// VPUNPCKLDQ: Unpack and Interleave Low-Order Doublewords into Quadwords.
//
// Forms:
//
// VPUNPCKLDQ m256 ymm ymm
// VPUNPCKLDQ ymm ymm ymm
// VPUNPCKLDQ m128 xmm xmm
// VPUNPCKLDQ xmm xmm xmm
// VPUNPCKLDQ m128 xmm k xmm
// VPUNPCKLDQ m256 ymm k ymm
// VPUNPCKLDQ xmm xmm k xmm
// VPUNPCKLDQ ymm ymm k ymm
// VPUNPCKLDQ m512 zmm k zmm
// VPUNPCKLDQ m512 zmm zmm
// VPUNPCKLDQ zmm zmm k zmm
// VPUNPCKLDQ zmm zmm zmm
func (amd64 *Amd64) VPUNPCKLDQ(r1, r2, r3 VectorRegister, comment ...string) {
amd64.writeOp(comment, "VPUNPCKLDQ", r1, r2, r3)
}

// VPUNPCKHDQ: Unpack and Interleave High-Order Doublewords into Quadwords.
//
// Forms:
//
// VPUNPCKHDQ m256 ymm ymm
// VPUNPCKHDQ ymm ymm ymm
// VPUNPCKHDQ m128 xmm xmm
// VPUNPCKHDQ xmm xmm xmm
// VPUNPCKHDQ m128 xmm k xmm
// VPUNPCKHDQ m256 ymm k ymm
// VPUNPCKHDQ xmm xmm k xmm
// VPUNPCKHDQ ymm ymm k ymm
// VPUNPCKHDQ m512 zmm k zmm
// VPUNPCKHDQ m512 zmm zmm
// VPUNPCKHDQ zmm zmm k zmm
// VPUNPCKHDQ zmm zmm zmm
func (amd64 *Amd64) VPUNPCKHDQ(r1, r2, r3 VectorRegister, comment ...string) {
amd64.writeOp(comment, "VPUNPCKHDQ", r1, r2, r3)
}

// VSHUFF64X2: Shuffle 128-Bit Packed Double-Precision Floating-Point Values.
//
// Forms:
//
// VSHUFF64X2 imm8 m256 ymm k ymm
// VSHUFF64X2 imm8 m256 ymm ymm
// VSHUFF64X2 imm8 ymm ymm k ymm
// VSHUFF64X2 imm8 ymm ymm ymm
// VSHUFF64X2 imm8 m512 zmm k zmm
// VSHUFF64X2 imm8 m512 zmm zmm
// VSHUFF64X2 imm8 zmm zmm k zmm
// VSHUFF64X2 imm8 zmm zmm zmm
func (amd64 *Amd64) VSHUFF64X2(imm8, r1, r2, r3 interface{}, comment ...string) {
amd64.writeOp(comment, "VSHUFF64X2", imm8, r1, r2, r3)
}

// VSHUFF32X4: Shuffle 128-Bit Packed Single-Precision Floating-Point Values.
//
// Forms:
Expand Down Expand Up @@ -421,6 +587,26 @@ func (amd64 *Amd64) VMOVDQU64k(r1, k, r2 interface{}, comment ...string) {
amd64.writeOp(comment, "VMOVDQU64", r1, k, r2)
}

// VPTERNLOGD: Bitwise Ternary Logical Operation on Doubleword Values.
//
// Forms:
//
// VPTERNLOGD imm8 m128 xmm k xmm
// VPTERNLOGD imm8 m128 xmm xmm
// VPTERNLOGD imm8 m256 ymm k ymm
// VPTERNLOGD imm8 m256 ymm ymm
// VPTERNLOGD imm8 xmm xmm k xmm
// VPTERNLOGD imm8 xmm xmm xmm
// VPTERNLOGD imm8 ymm ymm k ymm
// VPTERNLOGD imm8 ymm ymm ymm
// VPTERNLOGD imm8 m512 zmm k zmm
// VPTERNLOGD imm8 m512 zmm zmm
// VPTERNLOGD imm8 zmm zmm k zmm
// VPTERNLOGD imm8 zmm zmm zmm
func (amd64 *Amd64) VPTERNLOGD(imm8, r1, r2, r3 interface{}, comment ...string) {
amd64.writeOp(comment, "VPTERNLOGD", imm8, r1, r2, r3)
}

// VPADDQ Add Packed Quadword Integers
func (amd64 *Amd64) VPADDQ(r1, r2, r3 interface{}, comment ...string) {
amd64.writeOp(comment, "VPADDQ", r1, r2, r3)
Expand All @@ -441,6 +627,18 @@ func (amd64 *Amd64) VPANDQ(r1, r2, r3 interface{}, comment ...string) {
amd64.writeOp(comment, "VPANDQ", r1, r2, r3)
}

func (amd64 *Amd64) VPANDD(r1, r2, r3 interface{}, comment ...string) {
amd64.writeOp(comment, "VPANDD", r1, r2, r3)
}

func (amd64 *Amd64) VPANDDk(r1, r2, k, r3 interface{}, comment ...string) {
amd64.writeOp(comment, "VPANDD", r1, r2, k, r3)
}

func (amd64 *Amd64) VPANDDkz(r1, r2, k, r3 interface{}, comment ...string) {
amd64.writeOp(comment, "VPANDD.Z", r1, r2, k, r3)
}

// VPSRLQ Shift Packed Quadword Data Right Logical
func (amd64 *Amd64) VPSRLQ(r1, r2, r3 interface{}, comment ...string) {
amd64.writeOp(comment, "VPSRLQ", r1, r2, r3)
Expand Down Expand Up @@ -523,6 +721,11 @@ func (amd64 *Amd64) MOVQ(r1, r2 interface{}, comment ...string) {
}
}

// MOVD
func (amd64 *Amd64) MOVD(r1, r2 interface{}, comment ...string) {
amd64.writeOp(comment, "MOVD", r1, r2)
}

func (amd64 *Amd64) BTQ(r1, r2 interface{}, comment ...string) {
amd64.writeOp(comment, "BTQ", r1, r2)
}
Expand Down Expand Up @@ -714,8 +917,12 @@ func op(i interface{}) string {
switch t := i.(type) {
case string:
return t
case VectorRegister:
return string(t)
case Register:
return string(t)
case MaskRegister:
return string(t)
case int:
switch t {
case 0:
Expand Down
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