use python2 explicitly as python3 is default python now

.gitignore

@@ -1,3 +1,3 @@
 **/*.pyc
 *.o.*
-*.DS_Store
+*.DS_Store

.gitmodules

@@ -6,4 +6,4 @@
 	url = [email protected]:UAVCAN/dsdl.git
 [submodule "ChibiOS"]
 	path = ChibiOS
-	url = [email protected]:OpenMotorDrive/ChibiOS.git
+	url = [email protected]:CubePilot/ChibiOS.git

boards/com.hex.here_pro_1.0/board.h

@@ -1,6 +1,5 @@
 #pragma once
 
-#include <stdint.h>
 #include <modules/platform_stm32f767/platform_stm32f767.h>
 
 #define BOARD_CONFIG_HW_NAME "com.hex.here_pro"

boards/com.hex.here_pro_1.0/mcuconf.h

@@ -32,6 +32,7 @@
  */
 
 #define STM32F7xx_MCUCONF
+#define STM32F767_MCUCONF
 
 #define STM32_LSECLK                0U
 #define STM32_LSEDRV                (3U << 3U)

bootloader/Makefile

@@ -21,8 +21,7 @@ can \
 can_autobaud \
 uavcan \
 uavcan_nodestatus_publisher \
-uavcan_allocatee \
-usb_slcan
+uavcan_allocatee
 
 MESSAGES_ENABLED = \
 uavcan.protocol.GetNodeInfo \

bootloader/include/framework_conf.h

@@ -13,6 +13,7 @@
 #define UAVCAN_BEGINFIRMWAREUPDATE_SERVER_WORKER_THREAD lpwork_thread
 #define UAVCAN_ALLOCATEE_WORKER_THREAD                  lpwork_thread
 #define BOOTLOADER_APP_THREAD                           lpwork_thread
+#define LOGGER_WORKER_THREAD                            lpwork_thread
 #define USB_SLCAN_WORKER_THREAD                         can_thread
 
 #define CAN_TRX_WORKER_THREAD                           can_thread
@@ -29,9 +30,9 @@
 // Configure debug checks
 //
 
-#define CH_DBG_SYSTEM_STATE_CHECK           FALSE
-#define CH_DBG_ENABLE_CHECKS                FALSE
-#define CH_DBG_ENABLE_ASSERTS               FALSE
-#define CH_DBG_ENABLE_STACK_CHECK           FALSE
+#define CH_DBG_SYSTEM_STATE_CHECK           TRUE
+#define CH_DBG_ENABLE_CHECKS                TRUE
+#define CH_DBG_ENABLE_ASSERTS               TRUE
+#define CH_DBG_ENABLE_STACK_CHECK           TRUE
 
 #define CAN_TX_QUEUE_LEN 256

bootloader/openocd.cfg

@@ -1,4 +1,12 @@
-source [find interface/stlink-v2-1.cfg]
-source [find target/stm32f4x.cfg]
+source [find interface/stlink.cfg]
+source [find target/stm32h7x.cfg]
+reset_config srst_only separate connect_assert_srst
 $_TARGETNAME configure -rtos ChibiOS
+$_TARGETNAME configure -event gdb-attach {
+  halt
+}
+$_TARGETNAME configure -event gdb-attach {
+  reset init
+}
 init
+reset halt

bootloader/src/bootloader.c

@@ -171,7 +171,7 @@ static void begin_flash_from_path(uint8_t uavcan_idx, uint8_t source_node_id, co
     flash_state.source_node_id = source_node_id;
     flash_state.uavcan_idx = uavcan_idx;
     strncpy(flash_state.path, path, 200);
-    worker_thread_add_timer_task(&WT, &read_timeout_task, read_request_response_timeout, NULL, LL_MS2ST(500), false);
+    worker_thread_add_timer_task(&WT, &read_timeout_task, read_request_response_timeout, NULL, chTimeMS2I(500), false);
     do_send_read_request();
 
     corrupt_app();
@@ -201,12 +201,14 @@ static void file_read_response_handler(size_t msg_size, const void* buf, void* c
                 erase_app_page(i);
             }
         }
-        struct flash_write_buf_s buf = {res->data_len, (void*)res->data};
-        flash_write((void*)get_app_address_from_ofs(flash_state.ofs), 1, &buf);
 
         if (res->data_len < 256) {
+            struct flash_write_buf_s buf = {((res->data_len/FLASH_WORD_SIZE) + 1) * FLASH_WORD_SIZE, (void*)res->data};
+            flash_write((void*)get_app_address_from_ofs(flash_state.ofs), 1, &buf);
             on_update_complete();
         } else {
+            struct flash_write_buf_s buf = {res->data_len, (void*)res->data};
+            flash_write((void*)get_app_address_from_ofs(flash_state.ofs), 1, &buf);
             flash_state.ofs += res->data_len;
             do_send_read_request();
         }
@@ -219,7 +221,7 @@ static void do_resend_read_request(void) {
     strncpy((char*)read_req.path.path,flash_state.path,sizeof(read_req.path));
     read_req.path.path_len = strnlen(flash_state.path,sizeof(read_req.path));
     uavcan_request(flash_state.uavcan_idx, &uavcan_protocol_file_Read_req_descriptor, CANARD_TRANSFER_PRIORITY_HIGH, flash_state.source_node_id, &read_req);
-    worker_thread_timer_task_reschedule(&WT, &read_timeout_task, LL_MS2ST(500));
+    worker_thread_timer_task_reschedule(&WT, &read_timeout_task, chTimeMS2I(500));
     flash_state.retries++;
 }
 
@@ -341,7 +343,7 @@ static void check_and_start_boot_timer(void) {
         return;
     }
 
-    start_boot_timer(LL_S2ST((uint32_t)app_info.shared_app_parameters->boot_delay_sec));
+    start_boot_timer(chTimeS2I((uint32_t)app_info.shared_app_parameters->boot_delay_sec));
 }
 
 static void erase_app_page(uint32_t page_num) {
@@ -390,7 +392,7 @@ static void restart_req_handler(size_t msg_size, const void* buf, void* ctx) {
 
     if ((msg->magic_number == UAVCAN_PROTOCOL_RESTARTNODE_REQ_MAGIC_NUMBER) && system_get_restart_allowed()) {
         res.ok = true;
-        worker_thread_add_timer_task(&WT, &delayed_restart_task, delayed_restart_func, NULL, LL_MS2ST(1000), false);
+        worker_thread_add_timer_task(&WT, &delayed_restart_task, delayed_restart_func, NULL, chTimeMS2I(1000), false);
     }
 
     uavcan_respond(msg_wrapper->uavcan_idx, msg_wrapper, &res);

examples/basic_uavcan_functionality/Makefile

@@ -9,6 +9,8 @@ boot_msg \
 timing \
 system \
 pubsub \
+param \
+flash \
 worker_thread \
 can_driver_stm32 \
 can \
@@ -20,8 +22,7 @@ uavcan_beginfirmwareupdate_server \
 uavcan_allocatee \
 uavcan_restart \
 freemem_check \
-uavcan_timesync \
-logger
+uavcan_timesync
 
 MESSAGES_ENABLED = \
 uavcan.protocol.debug.LogMessage

examples/basic_uavcan_functionality/boards/com.hex.cube_orange_1.0/board.c

@@ -0,0 +1,8 @@
+#include <hal.h>
+
+void boardInit(void) {
+    rccResetAHB4(STM32_GPIO_EN_MASK);
+    rccEnableAHB4(STM32_GPIO_EN_MASK, true);
+    palSetLineMode(BOARD_PAL_LINE_CAN_RX, PAL_MODE_ALTERNATE(9) | PAL_STM32_OSPEED_MID2);
+    palSetLineMode(BOARD_PAL_LINE_CAN_TX, PAL_MODE_ALTERNATE(9) | PAL_STM32_OSPEED_MID2);
+}

examples/basic_uavcan_functionality/boards/com.hex.cube_orange_1.0/board.h

@@ -0,0 +1,20 @@
+#pragma once
+
+#include <modules/platform_stm32h743/platform_stm32h743.h>
+
+#define BOARD_FLASH_SIZE 2048
+
+#define BOARD_CONFIG_HW_NAME "com.hex.cube_orange"
+#define BOARD_CONFIG_HW_MAJOR_VER 1
+#define BOARD_CONFIG_HW_MINOR_VER 0
+
+#define BOARD_CONFIG_HW_INFO_STRUCTURE { \
+    .hw_name = BOARD_CONFIG_HW_NAME, \
+    .hw_major_version = BOARD_CONFIG_HW_MAJOR_VER, \
+    .hw_minor_version = BOARD_CONFIG_HW_MINOR_VER, \
+    .board_desc_fmt = SHARED_HW_INFO_BOARD_DESC_FMT_NONE, \
+    .board_desc = 0, \
+}
+
+#define BOARD_PAL_LINE_CAN_RX PAL_LINE(GPIOD,0)
+#define BOARD_PAL_LINE_CAN_TX PAL_LINE(GPIOD,1)

examples/basic_uavcan_functionality/boards/com.hex.cube_orange_1.0/board.mk

@@ -0,0 +1,4 @@
+BOARD_DIR := $(patsubst %/,%,$(dir $(lastword $(MAKEFILE_LIST))))
+BOARD_SRC = $(BOARD_DIR)/board.c
+BOARD_INC = $(BOARD_DIR)
+MODULES_ENABLED += platform_stm32h743

examples/basic_uavcan_functionality/boards/com.hex.cube_orange_1.0/mcuconf.h

@@ -0,0 +1,190 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+/*
+  this header is modelled on the one for the Nucleo-144 H743 board from ChibiOS
+ */
+#pragma once
+#define STM32H7xx_MCUCONF
+#define STM32H743_MCUCONF
+
+#define STM32_HSECLK 24000000U
+
+#define STM32_LSECLK 32768U
+
+#define STM32_LSEDRV (3U << 3U)
+
+/*
+ * General settings.
+ */
+#define STM32_NO_INIT                       FALSE
+#define STM32_SYS_CK_ENFORCED_VALUE         STM32_HSICLK
+
+/*
+ * Memory attributes settings.
+ */
+#define STM32_NOCACHE_SRAM1_SRAM2           FALSE
+#define STM32_NOCACHE_SRAM3                 TRUE
+
+/*
+ * PWR system settings.
+ * Reading STM32 Reference Manual is required.
+ * Register constants are taken from the ST header.
+ */
+#define STM32_VOS                           STM32_VOS_SCALE1
+#define STM32_PWR_CR1                       (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)
+#define STM32_PWR_CR2                       (PWR_CR2_BREN)
+#define STM32_PWR_CR3                       (PWR_CR3_LDOEN | PWR_CR3_USB33DEN)
+#define STM32_PWR_CPUCR                     0
+
+/*
+ * Clock tree static settings.
+ * Reading STM32 Reference Manual is required.
+ */
+#define STM32_HSI_ENABLED                   FALSE
+#define STM32_LSI_ENABLED                   FALSE
+#define STM32_CSI_ENABLED                   TRUE
+#define STM32_HSI48_ENABLED                 TRUE
+#define STM32_HSE_ENABLED                   TRUE
+#define STM32_LSE_ENABLED                   FALSE
+#define STM32_HSIDIV                        STM32_HSIDIV_DIV1
+
+/*
+ * PLLs static settings.
+ * Reading STM32 Reference Manual is required.
+ */
+#define STM32_PLLSRC                        STM32_PLLSRC_HSE_CK
+#define STM32_PLLCFGR_MASK                  ~0
+
+/*
+  setup PLLs based on HSE clock
+ */
+#if STM32_HSECLK == 8000000U
+// this gives 400MHz system clock
+#define STM32_PLL1_DIVM_VALUE               1
+#define STM32_PLL2_DIVM_VALUE               1
+#define STM32_PLL3_DIVM_VALUE               2
+#elif STM32_HSECLK == 16000000U
+// this gives 400MHz system clock
+#define STM32_PLL1_DIVM_VALUE               2
+#define STM32_PLL2_DIVM_VALUE               2
+#define STM32_PLL3_DIVM_VALUE               4
+#elif STM32_HSECLK == 24000000U
+// this gives 400MHz system clock
+#define STM32_PLL1_DIVM_VALUE               3
+#define STM32_PLL2_DIVM_VALUE               3
+#define STM32_PLL3_DIVM_VALUE               6
+#else
+#error "Unsupported HSE clock"
+#endif
+
+#if (STM32_HSECLK == 8000000U) || (STM32_HSECLK == 16000000U) || (STM32_HSECLK == 24000000U)
+// common clock tree for multiples of 8MHz crystals
+#define STM32_PLL1_DIVN_VALUE               100
+#define STM32_PLL1_DIVP_VALUE               2
+#define STM32_PLL1_DIVQ_VALUE               8
+#define STM32_PLL1_DIVR_VALUE               2
+
+#define STM32_PLL2_DIVN_VALUE               25
+#define STM32_PLL2_DIVP_VALUE               2
+#define STM32_PLL2_DIVQ_VALUE               2
+#define STM32_PLL2_DIVR_VALUE               2
+
+#define STM32_PLL3_DIVN_VALUE               72
+#define STM32_PLL3_DIVP_VALUE               3
+#define STM32_PLL3_DIVQ_VALUE               6
+#define STM32_PLL3_DIVR_VALUE               9
+#endif // 8MHz clock multiples
+
+#define STM32_PLL1_ENABLED                  TRUE
+#define STM32_PLL1_P_ENABLED                TRUE
+#define STM32_PLL1_Q_ENABLED                TRUE
+#define STM32_PLL1_R_ENABLED                TRUE
+#define STM32_PLL1_FRACN_VALUE              0
+
+#define STM32_PLL2_ENABLED                  TRUE
+#define STM32_PLL2_P_ENABLED                TRUE
+#define STM32_PLL2_Q_ENABLED                TRUE
+#define STM32_PLL2_R_ENABLED                TRUE
+#define STM32_PLL2_FRACN_VALUE              0
+
+#define STM32_PLL3_ENABLED                  TRUE
+#define STM32_PLL3_P_ENABLED                TRUE
+#define STM32_PLL3_Q_ENABLED                TRUE
+#define STM32_PLL3_R_ENABLED                TRUE
+#define STM32_PLL3_FRACN_VALUE              0
+
+/*
+ * Core clocks dynamic settings (can be changed at runtime).
+ * Reading STM32 Reference Manual is required.
+ */
+#define STM32_SW                            STM32_SW_PLL1_P_CK
+#define STM32_RTCSEL                        STM32_RTCSEL_NOCLK
+#define STM32_D1CPRE                        STM32_D1CPRE_DIV1
+#define STM32_D1HPRE                        STM32_D1HPRE_DIV4
+#define STM32_D1PPRE3                       STM32_D1PPRE3_DIV1
+#define STM32_D2PPRE1                       STM32_D2PPRE1_DIV1
+#define STM32_D2PPRE2                       STM32_D2PPRE2_DIV1
+#define STM32_D3PPRE4                       STM32_D3PPRE4_DIV1
+
+/*
+ * Peripherals clocks static settings.
+ * Reading STM32 Reference Manual is required.
+ */
+#define STM32_MCO1SEL                       STM32_MCO1SEL_HSE_CK
+#define STM32_MCO1PRE_VALUE                 4
+#define STM32_MCO2SEL                       STM32_MCO2SEL_SYS_CK
+#define STM32_MCO2PRE_VALUE                 4
+#define STM32_TIMPRE_ENABLE                 TRUE
+#define STM32_HRTIMSEL                      0
+#define STM32_STOPKERWUCK                   0
+#define STM32_STOPWUCK                      0
+#define STM32_RTCPRE_VALUE                  8
+#define STM32_CKPERSEL                      STM32_CKPERSEL_HSE_CK
+#define STM32_SDMMCSEL                      STM32_SDMMCSEL_PLL1_Q_CK
+#define STM32_QSPISEL                       STM32_QSPISEL_HCLK
+#define STM32_FMCSEL                        STM32_QSPISEL_HCLK
+#define STM32_SWPSEL                        STM32_SWPSEL_PCLK1
+#define STM32_FDCANSEL                      STM32_FDCANSEL_PLL1_Q_CK
+#define STM32_DFSDM1SEL                     STM32_DFSDM1SEL_PCLK2
+#define STM32_SPDIFSEL                      STM32_SPDIFSEL_PLL1_Q_CK
+#define STM32_SPI45SEL                      STM32_SPI45SEL_PLL2_Q_CK
+#define STM32_SPI123SEL                     STM32_SPI123SEL_PLL1_Q_CK
+#define STM32_SAI23SEL                      STM32_SAI23SEL_PLL1_Q_CK
+#define STM32_SAI1SEL                       STM32_SAI1SEL_PLL1_Q_CK
+#define STM32_LPTIM1SEL                     STM32_LPTIM1SEL_PCLK1
+#define STM32_CECSEL                        STM32_CECSEL_DISABLE
+#define STM32_USBSEL                        STM32_USBSEL_PLL3_Q_CK
+#define STM32_I2C123SEL                     STM32_I2C123SEL_PLL3_R_CK
+#define STM32_RNGSEL                        STM32_RNGSEL_HSI48_CK
+#define STM32_USART16SEL                    STM32_USART16SEL_PCLK2
+#define STM32_USART234578SEL                STM32_USART234578SEL_PCLK1
+#define STM32_SPI6SEL                       STM32_SPI6SEL_PLL2_Q_CK
+#define STM32_SAI4BSEL                      STM32_SAI4BSEL_PLL1_Q_CK
+#define STM32_SAI4ASEL                      STM32_SAI4ASEL_PLL1_Q_CK
+#define STM32_ADCSEL                        STM32_ADCSEL_PLL3_R_CK
+#define STM32_LPTIM345SEL                   STM32_LPTIM345SEL_PCLK4
+#define STM32_LPTIM2SEL                     STM32_LPTIM2SEL_PCLK4
+#define STM32_I2C4SEL                       STM32_I2C4SEL_PCLK4
+#define STM32_LPUART1SEL                    STM32_LPUART1SEL_PCLK4
+#define STM32_SDMMCSEL                      STM32_SDMMCSEL_PLL1_Q_CK
+
+#define STM32_CAN_CAN1_IRQ_PRIORITY         11
+
+/*
+ * ST driver system settings.
+ */
+#define STM32_ST_IRQ_PRIORITY               8
+#define STM32_ST_USE_TIMER                  2

examples/basic_uavcan_functionality/openocd.cfg

@@ -1,5 +1,7 @@
 source [find interface/stlink-v2-1.cfg]
-source [find target/stm32f3x.cfg]
+source [find target/stm32h7x.cfg]
+reset_config srst_only separate connect_assert_srst
+$_TARGETNAME configure
+# -rtos ChibiOS
 init
-reset run
-$_TARGETNAME configure -rtos ChibiOS
+#reset run

examples/driver_ak09916/src/ak09916_test.c

@@ -25,7 +25,7 @@ RUN_AFTER(INIT_END) {
         }
         usleep(10000);
     }
-    worker_thread_add_timer_task(&WT, &ak09916_test_task, ak09916_test_task_func, NULL, MS2ST(1), true);
+    worker_thread_add_timer_task(&WT, &ak09916_test_task, ak09916_test_task_func, NULL, chTimeMS2I(1), true);
 }
 
 static void ak09916_test_task_func(struct worker_thread_timer_task_s* task) {