zybo: fix PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY error in Vivado.

[svet-am]

The original ZYBO files had negative DQS values and this caused errors in Vivado. This is hardware errata as noted on Digilent site https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/reference-manual and Xilinx Answer Record 53039

[svet-am]

this is to fix the Vivado errors about PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY. By setting the values to 0.0, the designs passes Vivado with no errors and still works on the board.