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jywu-msftjywu-msft
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remove log spam from cpuinfo (microsoft#23548)
cpuinfo outputs error when cpu is not recognized. this has been a longstanding issue e.g. microsoft#21947 microsoft#21393 this issue has been exacerbated by microsoft#22856 this change https://github.com/microsoft/onnxruntime/blob/4fa0f1e0edb43141c68302859e410f2ec1232c3a/onnxruntime/core/mlas/lib/qnbitgemm_kernel_neon.cpp#L189 causes the messages to appear during static initialization. this means for python, when you import onnxruntime you immediately see the errors. ``` >>> import onnxruntime Error in cpuinfo: Unknown chip model name 'snapdragon (tm) 8cx gen 3 @ 3.40 GHz'. Please add new Windows on Arm SoC/chip support to arm/windows/init.c! unknown Qualcomm CPU part 0x1 ignored unknown Qualcomm CPU part 0x1 ignored unknown Qualcomm CPU part 0x1 ignored unknown Qualcomm CPU part 0x1 ignored unknown Qualcomm CPU part 0x1 ignored unknown Qualcomm CPU part 0x1 ignored unknown Qualcomm CPU part 0x1 ignored unknown Qualcomm CPU part 0x1 ignored unknown Qualcomm CPU part 0x1 ignored unknown Qualcomm CPU part 0x1 ignored unknown Qualcomm CPU part 0x1 ignored unknown Qualcomm CPU part 0x1 ignored ``` Fix is to patch pytorch_cpuinfo and to comment out std::cerr lines in cpuid_uarch.cc the errors are not actionable by the user, so they should not be emitted. tested that after these changes, these errors no longer show up.
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+42
-27
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3 files changed

+42
-27
lines changed

‎cmake/external/onnxruntime_external_deps.cmake

+2-2
Original file line numberDiff line numberDiff line change
@@ -357,8 +357,8 @@ if (CPUINFO_SUPPORTED)
357357
set(CPUINFO_BUILD_UNIT_TESTS OFF CACHE INTERNAL "")
358358
set(CPUINFO_BUILD_MOCK_TESTS OFF CACHE INTERNAL "")
359359
set(CPUINFO_BUILD_BENCHMARKS OFF CACHE INTERNAL "")
360-
if(onnxruntime_target_platform STREQUAL "ARM64EC")
361-
message(STATUS "Applying a patch for Windows ARM64EC in cpuinfo")
360+
if (onnxruntime_target_platform STREQUAL "ARM64EC" OR onnxruntime_target_platform STREQUAL "ARM64")
361+
message(STATUS "Applying a patch for Windows ARM64/ARM64EC in cpuinfo")
362362
FetchContent_Declare(
363363
pytorch_cpuinfo
364364
URL ${DEP_URL_pytorch_cpuinfo}

‎cmake/patches/cpuinfo/9bb12d342fd9479679d505d93a478a6f9cd50a47.patch

+14-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
diff --git a/include/cpuinfo.h b/include/cpuinfo.h
2-
index 03f2776..eaf6497 100644
2+
index 6eb4b8c..4346a5a 100644
33
--- a/include/cpuinfo.h
44
+++ b/include/cpuinfo.h
55
@@ -18,7 +18,7 @@
@@ -20,3 +20,16 @@ index 03f2776..eaf6497 100644
2020
#define CPUINFO_ARCH_ARM64 1
2121
#endif
2222

23+
diff --git a/src/arm/windows/init.c b/src/arm/windows/init.c
24+
index de2f6cc..c3a7835 100644
25+
--- a/src/arm/windows/init.c
26+
+++ b/src/arm/windows/init.c
27+
@@ -175,7 +175,7 @@ static struct woa_chip_info* get_system_info_from_registry(void) {
28+
if (chip_info == NULL) {
29+
/* No match was found, so print a warning and assign the unknown
30+
* case. */
31+
- cpuinfo_log_error(
32+
+ cpuinfo_log_debug(
33+
"Unknown chip model name '%ls'.\nPlease add new Windows on Arm SoC/chip support to arm/windows/init.c!",
34+
text_buffer);
35+
} else {

‎onnxruntime/core/common/cpuid_uarch.cc

+26-24
Original file line numberDiff line numberDiff line change
@@ -30,9 +30,11 @@ inline static uint32_t midr_get_part(uint32_t midr) {
3030
return (midr & CPUINFO_ARM_MIDR_PART_MASK) >> CPUINFO_ARM_MIDR_PART_OFFSET;
3131
}
3232

33+
#if 0
3334
inline static uint32_t midr_get_variant(uint32_t midr) {
3435
return (midr & CPUINFO_ARM_MIDR_VARIANT_MASK) >> CPUINFO_ARM_MIDR_VARIANT_OFFSET;
3536
}
37+
#endif
3638

3739
void decodeMIDR(
3840
uint32_t midr,
@@ -137,8 +139,8 @@ void decodeMIDR(
137139
*uarch = cpuinfo_uarch_arm11;
138140
break;
139141
// #endif /* ARM */
140-
default:
141-
std::cerr << "unknown ARM CPU part 0x" << std::hex << midr_get_part(midr) << " ignored\n";
142+
// default:
143+
// std::cerr << "unknown ARM CPU part 0x" << std::hex << midr_get_part(midr) << " ignored\n";
142144
}
143145
}
144146
break;
@@ -156,8 +158,8 @@ void decodeMIDR(
156158
*uarch = cpuinfo_uarch_thunderx2;
157159
break;
158160
// #endif
159-
default:
160-
std::cerr << "unknown Broadcom CPU part 0x" << std::hex << midr_get_part(midr) << " ignored\n";
161+
// default:
162+
// std::cerr << "unknown Broadcom CPU part 0x" << std::hex << midr_get_part(midr) << " ignored\n";
161163
}
162164
break;
163165
// #if (defined(_M_ARM64) || defined(__aarch64__)) && !defined(__ANDROID__)
@@ -172,8 +174,8 @@ void decodeMIDR(
172174
case 0x0AF: /* ThunderX2 99XX */
173175
*uarch = cpuinfo_uarch_thunderx2;
174176
break;
175-
default:
176-
std::cerr << "unknown Cavium CPU part 0x" << std::hex << midr_get_part(midr) << " ignored\n";
177+
// default:
178+
// std::cerr << "unknown Cavium CPU part 0x" << std::hex << midr_get_part(midr) << " ignored\n";
177179
}
178180
break;
179181
// #endif
@@ -187,8 +189,8 @@ void decodeMIDR(
187189
case 0xD40: /* Kirin 980 Big/Medium cores -> Cortex-A76 */
188190
*uarch = cpuinfo_uarch_cortex_a76;
189191
break;
190-
default:
191-
std::cerr << "unknown Huawei CPU part 0x" << std::hex << midr_get_part(midr) << " ignored\n";
192+
// default:
193+
// std::cerr << "unknown Huawei CPU part 0x" << std::hex << midr_get_part(midr) << " ignored\n";
192194
}
193195
break;
194196
// #if defined(_M_ARM) || defined(__arm__)
@@ -199,8 +201,8 @@ void decodeMIDR(
199201
case 6: /* PXA 3XX */
200202
*uarch = cpuinfo_uarch_xscale;
201203
break;
202-
default:
203-
std::cerr << "unknown Intel CPU part 0x" << std::hex << midr_get_part(midr) << " ignored\n";
204+
// default:
205+
// std::cerr << "unknown Intel CPU part 0x" << std::hex << midr_get_part(midr) << " ignored\n";
204206
}
205207
break;
206208
// #endif /* ARM */
@@ -215,8 +217,8 @@ void decodeMIDR(
215217
case 0x004:
216218
*uarch = cpuinfo_uarch_carmel;
217219
break;
218-
default:
219-
std::cerr << "unknown Nvidia CPU part 0x" << std::hex << midr_get_part(midr) << " ignored\n";
220+
// default:
221+
// std::cerr << "unknown Nvidia CPU part 0x" << std::hex << midr_get_part(midr) << " ignored\n";
220222
}
221223
break;
222224
#if !defined(__ANDROID__)
@@ -225,8 +227,8 @@ void decodeMIDR(
225227
case 0x000:
226228
*uarch = cpuinfo_uarch_xgene;
227229
break;
228-
default:
229-
std::cerr << "unknown Applied Micro CPU part 0x" << std::hex << midr_get_part(midr) << " ignored\n";
230+
// default:
231+
// std::cerr << "unknown Applied Micro CPU part 0x" << std::hex << midr_get_part(midr) << " ignored\n";
230232
}
231233
break;
232234
#endif
@@ -297,8 +299,8 @@ void decodeMIDR(
297299
*uarch = cpuinfo_uarch_saphira;
298300
break;
299301
// #endif /* ARM64 && !defined(__ANDROID__) */
300-
default:
301-
std::cerr << "unknown Qualcomm CPU part 0x" << std::hex << midr_get_part(midr) << " ignored\n";
302+
// default:
303+
// std::cerr << "unknown Qualcomm CPU part 0x" << std::hex << midr_get_part(midr) << " ignored\n";
302304
}
303305
break;
304306
case 'S':
@@ -343,10 +345,10 @@ void decodeMIDR(
343345
*/
344346
*uarch = cpuinfo_uarch_exynos_m5;
345347
break;
346-
default:
347-
std::cerr << "unknown Samsung CPU variant 0x"
348-
<< std::hex << midr_get_variant(midr) << " part 0x" << std::hex << midr_get_part(midr)
349-
<< " ignored\n";
348+
// default:
349+
// std::cerr << "unknown Samsung CPU variant 0x"
350+
//<< std::hex << midr_get_variant(midr) << " part 0x" << std::hex << midr_get_part(midr)
351+
//<< " ignored\n";
350352
}
351353
break;
352354
// #if defined(_M_ARM) || defined(__arm__)
@@ -356,13 +358,13 @@ void decodeMIDR(
356358
case 0x584: /* PJ4B-MP / PJ4C */
357359
*uarch = cpuinfo_uarch_pj4;
358360
break;
359-
default:
360-
std::cerr << "unknown Marvell CPU part 0x" << std::hex << midr_get_part(midr) << " ignored\n";
361+
// default:
362+
// std::cerr << "unknown Marvell CPU part 0x" << std::hex << midr_get_part(midr) << " ignored\n";
361363
}
362364
break;
363365
// #endif /* ARM */
364-
default:
365-
std::cerr << "unknown CPU uarch from MIDR value: 0x" << std::hex << midr << "\n";
366+
// default:
367+
// std::cerr << "unknown CPU uarch from MIDR value: 0x" << std::hex << midr << "\n";
366368
}
367369
}
368370

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