RISC-V: Add addi-x0 support for small immediates

Currently immediates in the range of -2**11 to 2**11-1 generate a lui 0 call. This can be optimized to addi x0 directly when setting a register. Signed-Off-By: Patrick O'Neill <[email protected]>
IBM · Jun 27, 2024 · 1965787 · 1965787
1 parent 300a542
commit 1965787
Showing 1 changed file with 5 additions and 0 deletions.
diff --git a/targets/riscv/isa/riscv-common/isa.py b/targets/riscv/isa/riscv-common/isa.py
@@ -163,6 +163,11 @@ def set_register(
                 )
                 instrs.append(addi)
 
+            elif value >= -(2**11) and value < (2**11):
+                addi = self.new_instruction("ADDI_V0")
+                addi.set_operands([value, self.registers["X0"], register])
+                instrs.append(addi)
+
             elif value >= -(2**31) and value < (2**31):
                 LOG.debug("Short path")